2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
25 "ADVANSUS", /* OEMID */
26 "A785E-I ", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
40 Name(HPBA, 0xFED00000) /* Base address of HPET table */
42 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44 /* USB overcurrent mapping pins. */
56 /* Some global data */
57 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
58 Name(OSV, Ones) /* Assume nothing */
59 Name(PMOD, One) /* Assume APIC */
65 Scope (\_PR) { /* define processor scope */
67 CPU0, /* name space name */
68 0, /* Unique number for this processor */
69 0x808, /* PBLK system I/O address !hardcoded! */
70 0x06 /* PBLKLEN for boot processor */
72 #include "acpi/cpstate.asl"
76 CPU1, /* name space name */
77 1, /* Unique number for this processor */
78 0x0000, /* PBLK system I/O address !hardcoded! */
79 0x00 /* PBLKLEN for boot processor */
81 #include "acpi/cpstate.asl"
85 CPU2, /* name space name */
86 2, /* Unique number for this processor */
87 0x0000, /* PBLK system I/O address !hardcoded! */
88 0x00 /* PBLKLEN for boot processor */
90 #include "acpi/cpstate.asl"
94 CPU3, /* name space name */
95 3, /* Unique number for this processor */
96 0x0000, /* PBLK system I/O address !hardcoded! */
97 0x00 /* PBLKLEN for boot processor */
99 #include "acpi/cpstate.asl"
101 } /* End _PR scope */
103 /* PIC IRQ mapping registers, C00h-C01h. */
104 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
105 Field(PRQM, ByteAcc, NoLock, Preserve) {
107 PRQD, 0x00000008, /* Offset: 1h */
109 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
110 PIRA, 0x00000008, /* Index 0 */
111 PIRB, 0x00000008, /* Index 1 */
112 PIRC, 0x00000008, /* Index 2 */
113 PIRD, 0x00000008, /* Index 3 */
114 PIRE, 0x00000008, /* Index 4 */
115 PIRF, 0x00000008, /* Index 5 */
116 PIRG, 0x00000008, /* Index 6 */
117 PIRH, 0x00000008, /* Index 7 */
120 /* PCI Error control register */
121 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
122 Field(PERC, ByteAcc, NoLock, Preserve) {
129 /* Client Management index/data registers */
130 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
131 Field(CMT, ByteAcc, NoLock, Preserve) {
133 /* Client Management Data register */
141 /* GPM Port register */
142 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
143 Field(GPT, ByteAcc, NoLock, Preserve) {
154 /* Flash ROM program enable register */
155 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
156 Field(FRE, ByteAcc, NoLock, Preserve) {
161 /* PM2 index/data registers */
162 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
163 Field(PM2R, ByteAcc, NoLock, Preserve) {
168 /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
169 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
170 Field(PIOR, ByteAcc, NoLock, Preserve) {
174 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
175 Offset(0x00), /* MiscControl */
179 Offset(0x01), /* MiscStatus */
183 Offset(0x04), /* SmiWakeUpEventEnable3 */
186 Offset(0x07), /* SmiWakeUpEventStatus3 */
189 Offset(0x10), /* AcpiEnable */
192 Offset(0x1C), /* ProgramIoEnable */
199 Offset(0x1D), /* IOMonitorStatus */
206 Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */
208 Offset(0x36), /* GEvtLevelConfig */
212 Offset(0x37), /* GPMLevelConfig0 */
219 Offset(0x38), /* GPMLevelConfig1 */
226 Offset(0x3B), /* PMEStatus1 */
235 Offset(0x55), /* SoftPciRst */
243 /* Offset(0x61), */ /* Options_1 */
247 Offset(0x65), /* UsbPMControl */
250 Offset(0x68), /* MiscEnable68 */
254 Offset(0x92), /* GEVENTIN */
257 Offset(0x96), /* GPM98IN */
260 Offset(0x9A), /* EnhanceControl */
263 Offset(0xA8), /* PIO7654Enable */
268 Offset(0xA9), /* PIO7654Status */
276 * First word is PM1_Status, Second word is PM1_Enable
278 OperationRegion(P1EB, SystemIO, APEB, 0x04)
279 Field(P1EB, ByteAcc, NoLock, Preserve) {
304 /* PCIe Configuration Space for 16 busses */
305 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
306 Field(PCFG, ByteAcc, NoLock, Preserve) {
307 /* Byte offsets are computed using the following technique:
308 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
309 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
311 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
313 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
324 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
327 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
329 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
331 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
333 P92E, 1, /* Port92 decode enable */
336 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
337 Field(SB5, AnyAcc, NoLock, Preserve){
339 Offset(0x120), /* Port 0 Task file status */
345 Offset(0x128), /* Port 0 Serial ATA status */
349 Offset(0x12C), /* Port 0 Serial ATA control */
351 Offset(0x130), /* Port 0 Serial ATA error */
356 offset(0x1A0), /* Port 1 Task file status */
362 Offset(0x1A8), /* Port 1 Serial ATA status */
366 Offset(0x1AC), /* Port 1 Serial ATA control */
368 Offset(0x1B0), /* Port 1 Serial ATA error */
373 Offset(0x220), /* Port 2 Task file status */
379 Offset(0x228), /* Port 2 Serial ATA status */
383 Offset(0x22C), /* Port 2 Serial ATA control */
385 Offset(0x230), /* Port 2 Serial ATA error */
390 Offset(0x2A0), /* Port 3 Task file status */
396 Offset(0x2A8), /* Port 3 Serial ATA status */
400 Offset(0x2AC), /* Port 3 Serial ATA control */
402 Offset(0x2B0), /* Port 3 Serial ATA error */
409 #include "acpi/routing.asl"
415 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
417 if(CondRefOf(\_OSI,Local1))
419 Store(1, OSTP) /* Assume some form of XP */
420 if (\_OSI("Windows 2006")) /* Vista */
425 If(WCMP(\_OS,"Linux")) {
426 Store(3, OSTP) /* Linux */
428 Store(4, OSTP) /* Gotta be WinCE */
434 Method(_PIC, 0x01, NotSerialized)
442 Method(CIRQ, 0x00, NotSerialized){
453 Name(IRQB, ResourceTemplate(){
454 IRQ(Level,ActiveLow,Shared){15}
457 Name(IRQP, ResourceTemplate(){
458 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
461 Name(PITF, ResourceTemplate(){
462 IRQ(Level,ActiveLow,Exclusive){9}
466 Name(_HID, EISAID("PNP0C0F"))
471 Return(0x0B) /* sata is invisible */
473 Return(0x09) /* sata is disabled */
475 } /* End Method(_SB.INTA._STA) */
478 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
480 } /* End Method(_SB.INTA._DIS) */
483 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
485 } /* Method(_SB.INTA._PRS) */
488 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
489 CreateWordField(IRQB, 0x1, IRQN)
490 ShiftLeft(1, PIRA, IRQN)
492 } /* Method(_SB.INTA._CRS) */
495 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
496 CreateWordField(ARG0, 1, IRQM)
498 /* Use lowest available IRQ */
499 FindSetRightBit(IRQM, Local0)
504 } /* End Method(_SB.INTA._SRS) */
505 } /* End Device(INTA) */
508 Name(_HID, EISAID("PNP0C0F"))
513 Return(0x0B) /* sata is invisible */
515 Return(0x09) /* sata is disabled */
517 } /* End Method(_SB.INTB._STA) */
520 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
522 } /* End Method(_SB.INTB._DIS) */
525 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
527 } /* Method(_SB.INTB._PRS) */
530 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
531 CreateWordField(IRQB, 0x1, IRQN)
532 ShiftLeft(1, PIRB, IRQN)
534 } /* Method(_SB.INTB._CRS) */
537 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
538 CreateWordField(ARG0, 1, IRQM)
540 /* Use lowest available IRQ */
541 FindSetRightBit(IRQM, Local0)
546 } /* End Method(_SB.INTB._SRS) */
547 } /* End Device(INTB) */
550 Name(_HID, EISAID("PNP0C0F"))
555 Return(0x0B) /* sata is invisible */
557 Return(0x09) /* sata is disabled */
559 } /* End Method(_SB.INTC._STA) */
562 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
564 } /* End Method(_SB.INTC._DIS) */
567 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
569 } /* Method(_SB.INTC._PRS) */
572 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
573 CreateWordField(IRQB, 0x1, IRQN)
574 ShiftLeft(1, PIRC, IRQN)
576 } /* Method(_SB.INTC._CRS) */
579 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
580 CreateWordField(ARG0, 1, IRQM)
582 /* Use lowest available IRQ */
583 FindSetRightBit(IRQM, Local0)
588 } /* End Method(_SB.INTC._SRS) */
589 } /* End Device(INTC) */
592 Name(_HID, EISAID("PNP0C0F"))
597 Return(0x0B) /* sata is invisible */
599 Return(0x09) /* sata is disabled */
601 } /* End Method(_SB.INTD._STA) */
604 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
606 } /* End Method(_SB.INTD._DIS) */
609 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
611 } /* Method(_SB.INTD._PRS) */
614 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
615 CreateWordField(IRQB, 0x1, IRQN)
616 ShiftLeft(1, PIRD, IRQN)
618 } /* Method(_SB.INTD._CRS) */
621 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
622 CreateWordField(ARG0, 1, IRQM)
624 /* Use lowest available IRQ */
625 FindSetRightBit(IRQM, Local0)
630 } /* End Method(_SB.INTD._SRS) */
631 } /* End Device(INTD) */
634 Name(_HID, EISAID("PNP0C0F"))
639 Return(0x0B) /* sata is invisible */
641 Return(0x09) /* sata is disabled */
643 } /* End Method(_SB.INTE._STA) */
646 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
648 } /* End Method(_SB.INTE._DIS) */
651 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
653 } /* Method(_SB.INTE._PRS) */
656 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
657 CreateWordField(IRQB, 0x1, IRQN)
658 ShiftLeft(1, PIRE, IRQN)
660 } /* Method(_SB.INTE._CRS) */
663 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
664 CreateWordField(ARG0, 1, IRQM)
666 /* Use lowest available IRQ */
667 FindSetRightBit(IRQM, Local0)
672 } /* End Method(_SB.INTE._SRS) */
673 } /* End Device(INTE) */
676 Name(_HID, EISAID("PNP0C0F"))
681 Return(0x0B) /* sata is invisible */
683 Return(0x09) /* sata is disabled */
685 } /* End Method(_SB.INTF._STA) */
688 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
690 } /* End Method(_SB.INTF._DIS) */
693 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
695 } /* Method(_SB.INTF._PRS) */
698 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
699 CreateWordField(IRQB, 0x1, IRQN)
700 ShiftLeft(1, PIRF, IRQN)
702 } /* Method(_SB.INTF._CRS) */
705 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
706 CreateWordField(ARG0, 1, IRQM)
708 /* Use lowest available IRQ */
709 FindSetRightBit(IRQM, Local0)
714 } /* End Method(_SB.INTF._SRS) */
715 } /* End Device(INTF) */
718 Name(_HID, EISAID("PNP0C0F"))
723 Return(0x0B) /* sata is invisible */
725 Return(0x09) /* sata is disabled */
727 } /* End Method(_SB.INTG._STA) */
730 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
732 } /* End Method(_SB.INTG._DIS) */
735 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
737 } /* Method(_SB.INTG._CRS) */
740 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
741 CreateWordField(IRQB, 0x1, IRQN)
742 ShiftLeft(1, PIRG, IRQN)
744 } /* Method(_SB.INTG._CRS) */
747 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
748 CreateWordField(ARG0, 1, IRQM)
750 /* Use lowest available IRQ */
751 FindSetRightBit(IRQM, Local0)
756 } /* End Method(_SB.INTG._SRS) */
757 } /* End Device(INTG) */
760 Name(_HID, EISAID("PNP0C0F"))
765 Return(0x0B) /* sata is invisible */
767 Return(0x09) /* sata is disabled */
769 } /* End Method(_SB.INTH._STA) */
772 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
774 } /* End Method(_SB.INTH._DIS) */
777 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
779 } /* Method(_SB.INTH._CRS) */
782 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
783 CreateWordField(IRQB, 0x1, IRQN)
784 ShiftLeft(1, PIRH, IRQN)
786 } /* Method(_SB.INTH._CRS) */
789 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
790 CreateWordField(ARG0, 1, IRQM)
792 /* Use lowest available IRQ */
793 FindSetRightBit(IRQM, Local0)
798 } /* End Method(_SB.INTH._SRS) */
799 } /* End Device(INTH) */
801 } /* End Scope(_SB) */
804 /* Supported sleep states: */
805 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
807 If (LAnd(SSFG, 0x01)) {
808 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
810 If (LAnd(SSFG, 0x02)) {
811 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
813 If (LAnd(SSFG, 0x04)) {
814 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
816 If (LAnd(SSFG, 0x08)) {
817 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
820 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
822 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
823 Name(CSMS, 0) /* Current System State */
825 /* Wake status package */
826 Name(WKST,Package(){Zero, Zero})
829 * \_PTS - Prepare to Sleep method
832 * Arg0=The value of the sleeping state S1=1, S2=2, etc
837 * The _PTS control method is executed at the beginning of the sleep process
838 * for S1-S5. The sleeping value is passed to the _PTS control method. This
839 * control method may be executed a relatively long time before entering the
840 * sleep state and the OS may abort the operation without notification to
841 * the ACPI driver. This method cannot modify the configuration or power
842 * state of any device in the system.
845 /* DBGO("\\_PTS\n") */
846 /* DBGO("From S0 to S") */
850 /* Don't allow PCIRST# to reset USB */
855 /* Clear sleep SMI status flag and enable sleep SMI trap. */
859 /* On older chips, clear PciExpWakeDisEn */
860 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
865 /* Clear wake status structure. */
866 Store(0, Index(WKST,0))
867 Store(0, Index(WKST,1))
868 } /* End Method(\_PTS) */
871 * The following method results in a "not a valid reserved NameSeg"
872 * warning so I have commented it out for the duration. It isn't
873 * used, so it could be removed.
876 * \_GTS OEM Going To Sleep method
879 * Arg0=The value of the sleeping state S1=1, S2=2
886 * DBGO("From S0 to S")
893 * \_BFS OEM Back From Sleep method
896 * Arg0=The value of the sleeping state S1=1, S2=2
902 /* DBGO("\\_BFS\n") */
905 /* DBGO(" to S0\n") */
909 * \_WAK System Wake method
912 * Arg0=The value of the sleeping state S1=1, S2=2
915 * Return package of 2 DWords
917 * 0x00000000 wake succeeded
918 * 0x00000001 Wake was signaled but failed due to lack of power
919 * 0x00000002 Wake was signaled but failed due to thermal condition
920 * Dword 2 - Power Supply state
921 * if non-zero the effective S-state the power supply entered
924 /* DBGO("\\_WAK\n") */
927 /* DBGO(" to S0\n") */
932 /* Restore PCIRST# so it resets USB */
937 /* Arbitrarily clear PciExpWakeStatus */
940 /* if(DeRefOf(Index(WKST,0))) {
941 * Store(0, Index(WKST,1))
943 * Store(Arg0, Index(WKST,1))
947 } /* End Method(\_WAK) */
949 Scope(\_GPE) { /* Start Scope GPE */
950 /* General event 0 */
952 * DBGO("\\_GPE\\_L00\n")
956 /* General event 1 */
958 * DBGO("\\_GPE\\_L00\n")
962 /* General event 2 */
964 * DBGO("\\_GPE\\_L00\n")
968 /* General event 3 */
970 /* DBGO("\\_GPE\\_L00\n") */
971 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
974 /* General event 4 */
976 * DBGO("\\_GPE\\_L00\n")
980 /* General event 5 */
982 * DBGO("\\_GPE\\_L00\n")
986 /* General event 6 - Used for GPM6, moved to USB.asl */
988 * DBGO("\\_GPE\\_L00\n")
992 /* General event 7 - Used for GPM7, moved to USB.asl */
994 * DBGO("\\_GPE\\_L07\n")
998 /* Legacy PM event */
1000 /* DBGO("\\_GPE\\_L08\n") */
1003 /* Temp warning (TWarn) event */
1005 /* DBGO("\\_GPE\\_L09\n") */
1006 /* Notify (\_TZ.TZ00, 0x80) */
1011 * DBGO("\\_GPE\\_L0A\n")
1015 /* USB controller PME# */
1017 /* DBGO("\\_GPE\\_L0B\n") */
1018 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1019 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1020 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1021 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1022 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1023 Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
1024 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1025 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1028 /* AC97 controller PME# */
1030 * DBGO("\\_GPE\\_L0C\n")
1034 /* OtherTherm PME# */
1036 * DBGO("\\_GPE\\_L0D\n")
1040 /* GPM9 SCI event - Moved to USB.asl */
1042 * DBGO("\\_GPE\\_L0E\n")
1046 /* PCIe HotPlug event */
1048 * DBGO("\\_GPE\\_L0F\n")
1052 /* ExtEvent0 SCI event */
1054 /* DBGO("\\_GPE\\_L10\n") */
1058 /* ExtEvent1 SCI event */
1060 /* DBGO("\\_GPE\\_L11\n") */
1063 /* PCIe PME# event */
1065 * DBGO("\\_GPE\\_L12\n")
1069 /* GPM0 SCI event - Moved to USB.asl */
1071 * DBGO("\\_GPE\\_L13\n")
1075 /* GPM1 SCI event - Moved to USB.asl */
1077 * DBGO("\\_GPE\\_L14\n")
1081 /* GPM2 SCI event - Moved to USB.asl */
1083 * DBGO("\\_GPE\\_L15\n")
1087 /* GPM3 SCI event - Moved to USB.asl */
1089 * DBGO("\\_GPE\\_L16\n")
1093 /* GPM8 SCI event - Moved to USB.asl */
1095 * DBGO("\\_GPE\\_L17\n")
1099 /* GPIO0 or GEvent8 event */
1101 /* DBGO("\\_GPE\\_L18\n") */
1102 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1103 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1104 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1105 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1106 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1107 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1110 /* GPM4 SCI event - Moved to USB.asl */
1112 * DBGO("\\_GPE\\_L19\n")
1116 /* GPM5 SCI event - Moved to USB.asl */
1118 * DBGO("\\_GPE\\_L1A\n")
1122 /* Azalia SCI event */
1124 /* DBGO("\\_GPE\\_L1B\n") */
1125 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1126 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1129 /* GPM6 SCI event - Reassigned to _L06 */
1131 * DBGO("\\_GPE\\_L1C\n")
1135 /* GPM7 SCI event - Reassigned to _L07 */
1137 * DBGO("\\_GPE\\_L1D\n")
1141 /* GPIO2 or GPIO66 SCI event */
1143 * DBGO("\\_GPE\\_L1E\n")
1147 /* SATA SCI event - Moved to sata.asl */
1149 * DBGO("\\_GPE\\_L1F\n")
1153 } /* End Scope GPE */
1155 #include "acpi/usb.asl"
1158 Scope(\_SB) { /* Start \_SB scope */
1159 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1162 /* Note: Only need HID on Primary Bus */
1166 Name(_HID, EISAID("PNP0A03"))
1167 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1168 Method(_BBN, 0) { /* Bus number = 0 */
1172 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1173 Return(0x0B) /* Status is visible */
1177 If(PMOD){ Return(APR0) } /* APIC mode */
1178 Return (PR0) /* PIC Mode */
1181 /* Describe the Northbridge devices */
1183 Name(_ADR, 0x00000000)
1186 /* The internal GFX bridge */
1188 Name(_ADR, 0x00010000)
1189 Name(_PRW, Package() {0x18, 4})
1195 /* The external GFX bridge */
1197 Name(_ADR, 0x00020000)
1198 Name(_PRW, Package() {0x18, 4})
1200 If(PMOD){ Return(APS2) } /* APIC mode */
1201 Return (PS2) /* PIC Mode */
1205 /* Dev3 is also an external GFX bridge, not used in Herring */
1208 Name(_ADR, 0x00040000)
1209 Name(_PRW, Package() {0x18, 4})
1211 If(PMOD){ Return(APS4) } /* APIC mode */
1212 Return (PS4) /* PIC Mode */
1217 Name(_ADR, 0x00050000)
1218 Name(_PRW, Package() {0x18, 4})
1220 If(PMOD){ Return(APS5) } /* APIC mode */
1221 Return (PS5) /* PIC Mode */
1226 Name(_ADR, 0x00060000)
1227 Name(_PRW, Package() {0x18, 4})
1229 If(PMOD){ Return(APS6) } /* APIC mode */
1230 Return (PS6) /* PIC Mode */
1234 /* The onboard EtherNet chip */
1236 Name(_ADR, 0x00070000)
1237 Name(_PRW, Package() {0x18, 4})
1239 If(PMOD){ Return(APS7) } /* APIC mode */
1240 Return (PS7) /* PIC Mode */
1246 Name(_ADR, 0x00090000)
1247 Name(_PRW, Package() {0x18, 4})
1249 If(PMOD){ Return(APS9) } /* APIC mode */
1250 Return (PS9) /* PIC Mode */
1255 Name(_ADR, 0x000A0000)
1256 Name(_PRW, Package() {0x18, 4})
1258 If(PMOD){ Return(APSa) } /* APIC mode */
1259 Return (PSa) /* PIC Mode */
1264 Name(_ADR, 0x00150000)
1265 Name(_PRW, Package() {0x18, 4})
1267 If(PMOD){ Return(APE0) } /* APIC mode */
1268 Return (PE0) /* PIC Mode */
1272 Name(_ADR, 0x00150001)
1273 Name(_PRW, Package() {0x18, 4})
1275 If(PMOD){ Return(APE1) } /* APIC mode */
1276 Return (PE1) /* PIC Mode */
1280 Name(_ADR, 0x00150002)
1281 Name(_PRW, Package() {0x18, 4})
1283 If(PMOD){ Return(APE2) } /* APIC mode */
1284 Return (APE2) /* PIC Mode */
1288 Name(_ADR, 0x00150003)
1289 Name(_PRW, Package() {0x18, 4})
1291 If(PMOD){ Return(APE3) } /* APIC mode */
1292 Return (PE3) /* PIC Mode */
1296 /* PCI slot 1, 2, 3 */
1298 Name(_ADR, 0x00140004)
1299 Name(_PRW, Package() {0x18, 4})
1306 /* Describe the Southbridge devices */
1308 Name(_ADR, 0x00110000)
1309 #include "acpi/sata.asl"
1313 Name(_ADR, 0x00120000)
1314 Name(_PRW, Package() {0x0B, 3})
1318 Name(_ADR, 0x00120002)
1319 Name(_PRW, Package() {0x0B, 3})
1323 Name(_ADR, 0x00130000)
1324 Name(_PRW, Package() {0x0B, 3})
1328 Name(_ADR, 0x00130002)
1329 Name(_PRW, Package() {0x0B, 3})
1333 Name(_ADR, 0x00160000)
1334 Name(_PRW, Package() {0x0B, 3})
1338 Name(_ADR, 0x00160002)
1339 Name(_PRW, Package() {0x0B, 3})
1343 Name(_ADR, 0x00140005)
1344 Name(_PRW, Package() {0x0B, 3})
1348 Name(_ADR, 0x00140000)
1351 /* Primary (and only) IDE channel */
1353 Name(_ADR, 0x00140001)
1354 #include "acpi/ide.asl"
1358 Name(_ADR, 0x00140002)
1359 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1360 Field(AZPD, AnyAcc, NoLock, Preserve) {
1384 If(LEqual(OSTP,3)){ /* If we are running Linux */
1393 Name(_ADR, 0x00140003)
1395 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1396 } */ /* End Method(_SB.SBRDG._INI) */
1398 /* Real Time Clock Device */
1400 Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */
1401 Name(_CRS, ResourceTemplate() {
1403 IO(Decode16,0x0070, 0x0070, 0, 2)
1404 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1406 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1408 Device(TMR) { /* Timer */
1409 Name(_HID,EISAID("PNP0100")) /* System Timer */
1410 Name(_CRS, ResourceTemplate() {
1412 IO(Decode16, 0x0040, 0x0040, 0, 4)
1413 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1415 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1417 Device(SPKR) { /* Speaker */
1418 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1419 Name(_CRS, ResourceTemplate() {
1420 IO(Decode16, 0x0061, 0x0061, 0, 1)
1422 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1425 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1426 Name(_CRS, ResourceTemplate() {
1428 IO(Decode16,0x0020, 0x0020, 0, 2)
1429 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1430 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1431 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1433 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1435 Device(MAD) { /* 8257 DMA */
1436 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1437 Name(_CRS, ResourceTemplate() {
1438 DMA(Compatibility,BusMaster,Transfer8){4}
1439 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1440 IO(Decode16, 0x0081, 0x0081, 0x00, 0x03)
1441 IO(Decode16, 0x0087, 0x0087, 0x00, 0x01)
1442 IO(Decode16, 0x0089, 0x0089, 0x00, 0x03)
1443 IO(Decode16, 0x008F, 0x008F, 0x00, 0x01)
1444 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1445 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1446 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1449 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1450 Name(_CRS, ResourceTemplate() {
1451 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1454 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1457 Name(_HID,EISAID("PNP0103"))
1458 Name(CRS,ResourceTemplate() {
1459 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1462 Return(0x0F) /* sata is visible */
1465 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1469 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1474 Name(_ADR, 0x00140004)
1475 } /* end HostPciBr */
1478 Name(_ADR, 0x00140005)
1479 } /* end Ac97audio */
1482 Name(_ADR, 0x00140006)
1483 } /* end Ac97modem */
1485 Name(CRES, ResourceTemplate() {
1486 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1488 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1489 0x0000, /* address granularity */
1490 0x0000, /* range minimum */
1491 0x0CF7, /* range maximum */
1492 0x0000, /* translation */
1496 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1497 0x0000, /* address granularity */
1498 0x0D00, /* range minimum */
1499 0xFFFF, /* range maximum */
1500 0x0000, /* translation */
1504 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1505 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1506 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1507 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1509 /* DRAM Memory from 1MB to TopMem */
1510 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1512 /* BIOS space just below 4GB */
1514 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1515 0x00, /* Granularity */
1516 0x00000000, /* Min */
1517 0x00000000, /* Max */
1518 0x00000000, /* Translation */
1519 0x00000000, /* Max-Min, RLEN */
1524 /* DRAM memory from 4GB to TopMem2 */
1525 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1526 0xFFFFFFFF, /* Granularity */
1527 0x00000000, /* Min */
1528 0x00000000, /* Max */
1529 0x00000000, /* Translation */
1530 0x00000000, /* Max-Min, RLEN */
1535 /* BIOS space just below 16EB */
1536 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1537 0xFFFFFFFF, /* Granularity */
1538 0x00000000, /* Min */
1539 0x00000000, /* Max */
1540 0x00000000, /* Translation */
1541 0x00000000, /* Max-Min, RLEN */
1546 /* memory space for PCI BARs below 4GB */
1547 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1548 }) /* End Name(_SB.PCI0.CRES) */
1551 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1553 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1554 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1555 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1556 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1557 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1558 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1560 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1561 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1562 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1563 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1565 If(LGreater(LOMH, 0xC0000)){
1566 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1567 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1570 /* Set size of memory from 1MB to TopMem */
1571 Subtract(TOM1, 0x100000, DMLL)
1574 * If(LNotEqual(TOM2, 0x00000000)){
1575 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1576 * Subtract(TOM2, 0x100000000, DMHL)
1580 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1581 If(LEqual(TOM2, 0x00000000)){
1582 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1585 Else { /* Otherwise, put the BIOS just below 16EB */
1586 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1590 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1591 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1593 * Declare memory between TOM1 and 4GB as available
1595 * Use ShiftLeft to avoid 64bit constant (for XP).
1596 * This will work even if the OS does 32bit arithmetic, as
1597 * 32bit (0x00000000 - TOM1) will wrap and give the same
1598 * result as 64bit (0x100000000 - TOM1).
1601 ShiftLeft(0x10000000, 4, Local0)
1602 Subtract(Local0, TOM1, Local0)
1605 Return(CRES) /* note to change the Name buffer */
1606 } /* end of Method(_SB.PCI0._CRS) */
1610 * FIRST METHOD CALLED UPON BOOT
1612 * 1. If debugging, print current OS and ACPI interpreter.
1613 * 2. Get PCI Interrupt routing from ACPI VSM, this
1614 * value is based on user choice in BIOS setup.
1617 /* DBGO("\\_SB\\_INI\n") */
1618 /* DBGO(" DSDT.ASL code from ") */
1619 /* DBGO(__DATE__) */
1621 /* DBGO(__TIME__) */
1622 /* DBGO("\n Sleep states supported: ") */
1624 /* DBGO(" \\_OS=") */
1626 /* DBGO("\n \\_REV=") */
1630 /* Determine the OS we're running on */
1633 /* On older chips, clear PciExpWakeDisEn */
1634 /*if (LLessEqual(\SBRI, 0x13)) {
1638 } /* End Method(_SB._INI) */
1639 } /* End Device(PCI0) */
1641 Device(PWRB) { /* Start Power button device */
1642 Name(_HID, EISAID("PNP0C0C"))
1644 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1645 Name(_STA, 0x0B) /* sata is invisible */
1647 } /* End \_SB scope */
1651 /* DBGO("\\_SI\\_SST\n") */
1652 /* DBGO(" New Indicator state: ") */
1656 } /* End Scope SI */
1660 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1661 Field (SMB0, ByteAcc, NoLock, Preserve) {
1662 HSTS, 8, /* SMBUS status */
1663 SSTS, 8, /* SMBUS slave status */
1664 HCNT, 8, /* SMBUS control */
1665 HCMD, 8, /* SMBUS host cmd */
1666 HADD, 8, /* SMBUS address */
1667 DAT0, 8, /* SMBUS data0 */
1668 DAT1, 8, /* SMBUS data1 */
1669 BLKD, 8, /* SMBUS block data */
1670 SCNT, 8, /* SMBUS slave control */
1671 SCMD, 8, /* SMBUS shaow cmd */
1672 SEVT, 8, /* SMBUS slave event */
1673 SDAT, 8 /* SMBUS slave data */
1676 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1678 Store (0xFA, Local0)
1679 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1687 Method (SWTC, 1, NotSerialized) {
1688 Store (Arg0, Local0)
1689 Store (0x07, Local2)
1691 While (LEqual (Local1, One)) {
1692 Store (And (HSTS, 0x1E), Local3)
1693 If (LNotEqual (Local3, Zero)) { /* read sucess */
1694 If (LEqual (Local3, 0x02)) {
1695 Store (Zero, Local2)
1698 Store (Zero, Local1)
1701 If (LLess (Local0, 0x0A)) { /* read failure */
1702 Store (0x10, Local2)
1703 Store (Zero, Local1)
1706 Sleep (0x0A) /* 10 ms, try again */
1707 Subtract (Local0, 0x0A, Local0)
1715 Method (SMBR, 3, NotSerialized) {
1716 Store (0x07, Local0)
1717 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1718 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1719 If (LEqual (Local0, Zero)) {
1725 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1727 If (LEqual (Arg0, 0x07)) {
1728 Store (0x48, HCNT) /* read byte */
1731 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1732 If (LEqual (Local1, Zero)) {
1733 If (LEqual (Arg0, 0x07)) {
1734 Store (DAT0, Local0)
1738 Store (Local1, Local0)
1744 /* DBGO("the value of SMBusData0 register ") */
1760 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1761 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1762 Return(Add(0, 2730))
1764 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1765 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1766 Return(Package() {\_TZ.TZ00.FAN0})
1769 Name(_HID, EISAID("PNP0C0B"))
1770 Name(_PR0, Package() {PFN0})
1773 PowerResource(PFN0,0,0) {
1779 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1782 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1786 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1787 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1788 Return (Add (THOT, KELV))
1790 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1791 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1792 Return (Add (TCRT, KELV))
1794 Method(_TMP,0) { /* return current temp of this zone */
1795 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1796 If (LGreater (Local0, 0x10)) {
1797 Store (Local0, Local1)
1800 Add (Local0, THOT, Local0)
1801 Return (Add (400, KELV))
1804 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1805 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1806 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1807 If (LGreater (Local0, 0x10)) {
1808 If (LGreater (Local0, Local1)) {
1809 Store (Local0, Local1)
1812 Multiply (Local1, 10, Local1)
1813 Return (Add (Local1, KELV))
1816 Add (Local0, THOT, Local0)
1817 Return (Add (400 , KELV))
1824 /* End of ASL file */