src/mainboard/Makefile.romccboard.inc

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
   5 ## Copyright (C) 2010 coresystems GmbH
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 initobj-y += crt0.o
  23
  24 crt0s :=
  25 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
  26 crt0s += $(src)/cpu/x86/16bit/entry16.inc
  27 endif
  28 crt0s += $(src)/cpu/x86/32bit/entry32.inc
  29 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
  30 crt0s += $(src)/cpu/x86/16bit/reset16.inc
  31 crt0s += $(src)/arch/i386/lib/cpu_reset.inc
  32 crt0s += $(src)/arch/i386/lib/id.inc
  33 endif
  34 crt0s += $(src)/cpu/x86/fpu_enable.inc
  35 ifeq ($(CONFIG_CPU_AMD_GX1),y)
  36 crt0s += $(src)/cpu/amd/model_gx1/cpu_setup.inc
  37 crt0s += $(src)/cpu/amd/model_gx1/gx_setup.inc
  38 endif
  39 ifeq ($(CONFIG_SSE),y)
  40 crt0s += $(src)/cpu/x86/sse_enable.inc
  41 endif
  42 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
  43 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc
  44 endif
  45 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
  46 ifeq ($(CONFIG_SSE),y)
  47 crt0s += $(src)/cpu/x86/sse_disable.inc
  48 endif
  49 ifeq ($(CONFIG_MMX),y)
  50 crt0s += $(src)/cpu/x86/mmx_disable.inc
  51 endif
  52
  53 ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
  54 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
  55 ldscripts += $(src)/cpu/x86/16bit/entry16.lds
  56 endif
  57 ldscripts += $(src)/cpu/x86/32bit/entry32.lds
  58 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
  59 ldscripts += $(src)/cpu/x86/16bit/reset16.lds
  60 ldscripts += $(src)/arch/i386/lib/id.lds
  61 ldscripts += $(src)/arch/i386/lib/failover.lds
  62 endif
  63
  64 driver-y += mainboard.o
  65
  66 obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
  67 obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
  68 obj-$(CONFIG_HAVE_HARD_RESET) += reset.o
  69
  70 ifdef POST_EVALUATION
  71
  72 ROMCCFLAGS ?= -mcpu=p2 -O2
  73
  74 $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
  75         $(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
  76
  77 ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
  78 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h $(obj)/build.h
  79         $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
  80 else
  81 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h
  82         $(obj)/romcc $(ROMCCFLAGS) $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@
  83 endif
  84
  85 endif
  86