src/mainboard/Iwill/DK8S2/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <arch/cpu.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "northbridge/amd/amdk8/incoherent_ht.c"
  15 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "lib/delay.c"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "northbridge/amd/amdk8/cpu_rev.c"
  23 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  24 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 static void hard_reset(void)
  30 {
  31         set_bios_reset();
  32
  33         /* enable cf9 */
  34         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  35         /* reset */
  36         outb(0x0e, 0x0cf9);
  37 }
  38
  39 static void soft_reset(void)
  40 {
  41         set_bios_reset();
  42         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  43 }
  44
  45 /*
  46  * GPIO28 of 8111 will control H0_MEMRESET_L
  47  * GPIO29 of 8111 will control H1_MEMRESET_L
  48  */
  49 static void memreset_setup(void)
  50 {
  51         if (is_cpu_pre_c0()) {
  52                 /* Set the memreset low */
  53                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  54                 /* Ensure the BIOS has control of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  56         } else {
  57                 /* Ensure the CPU has controll of the memory lines */
  58                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  59         }
  60 }
  61
  62 static void memreset(int controllers, const struct mem_controller *ctrl)
  63 {
  64         if (is_cpu_pre_c0()) {
  65                 udelay(800);
  66                 /* Set memreset_high */
  67                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  68                 udelay(90);
  69         }
  70 }
  71
  72 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  73 {
  74         /* Routing Table Node i
  75          *
  76          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  77          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  78          *
  79          * [ 0: 3] Request Route
  80          *     [0] Route to this node
  81          *     [1] Route to Link 0
  82          *     [2] Route to Link 1
  83          *     [3] Route to Link 2
  84          * [11: 8] Response Route
  85          *     [0] Route to this node
  86          *     [1] Route to Link 0
  87          *     [2] Route to Link 1
  88          *     [3] Route to Link 2
  89          * [19:16] Broadcast route
  90          *     [0] Route to this node
  91          *     [1] Route to Link 0
  92          *     [2] Route to Link 1
  93          *     [3] Route to Link 2
  94          */
  95
  96         uint32_t ret=0x00010101; /* default row entry */
  97
  98         static const unsigned int rows_2p[2][2] = {
  99                 { 0x00050101, 0x00010404 },
 100                 { 0x00010404, 0x00050101 }
 101         };
 102
 103         if(maxnodes>2) {
 104                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 105                 maxnodes=2;
 106         }
 107
 108         if (!(node>=maxnodes || row>=maxnodes)) {
 109                 ret=rows_2p[node][row];
 110         }
 111
 112         return ret;
 113 }
 114
 115 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 116 {
 117         /* nothing to do */
 118 }
 119
 120 static inline int spd_read_byte(unsigned device, unsigned address)
 121 {
 122         return smbus_read_byte(device, address);
 123 }
 124
 125 #include "northbridge/amd/amdk8/raminit.c"
 126 #include "northbridge/amd/amdk8/coherent_ht.c"
 127 #include "sdram/generic_sdram.c"
 128 #include "northbridge/amd/amdk8/resourcemap.c"
 129
 130 #define FIRST_CPU  1
 131 #define SECOND_CPU 1
 132 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 133 static void main(unsigned long bist)
 134 {
 135         static const struct mem_controller cpu[] = {
 136 #if FIRST_CPU
 137                 {
 138                         .node_id = 0,
 139                         .f0 = PCI_DEV(0, 0x18, 0),
 140                         .f1 = PCI_DEV(0, 0x18, 1),
 141                         .f2 = PCI_DEV(0, 0x18, 2),
 142                         .f3 = PCI_DEV(0, 0x18, 3),
 143                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 144                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 145                 },
 146 #endif
 147 #if SECOND_CPU
 148                 {
 149                         .node_id = 1,
 150                         .f0 = PCI_DEV(0, 0x19, 0),
 151                         .f1 = PCI_DEV(0, 0x19, 1),
 152                         .f2 = PCI_DEV(0, 0x19, 2),
 153                         .f3 = PCI_DEV(0, 0x19, 3),
 154                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 155                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 156                 },
 157 #endif
 158         };
 159
 160         int needs_reset;
 161         unsigned nodeid;
 162
 163         if (bist == 0) {
 164                 /* Skip this if there was a built in self test failure */
 165                 amd_early_mtrr_init();
 166                 enable_lapic();
 167                 init_timer();
 168
 169                 /* Has this cpu already booted? */
 170                 if (cpu_init_detected(nodeid)) {
 171                         asm volatile ("jmp __cpu_reset");
 172                 }
 173                 distinguish_cpu_resets(nodeid);
 174                 if (!boot_cpu()) {
 175                         stop_this_cpu();
 176                 }
 177         }
 178         /* Setup the console */
 179         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 180         uart_init();
 181         console_init();
 182
 183         /* Halt if there was a built in self test failure */
 184         report_bist_failure(bist);
 185
 186         setup_default_resource_map();
 187         needs_reset = setup_coherent_ht_domain();
 188         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 189         if (needs_reset) {
 190                 print_info("ht reset -\r\n");
 191                 soft_reset();
 192         }
 193
 194 #if 0
 195         print_pci_devices();
 196 #endif
 197
 198         enable_smbus();
 199
 200 #if 0
 201         dump_spd_registers(&cpu[0]);
 202 #endif
 203
 204         memreset_setup();
 205         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 206
 207 #if 0
 208         dump_pci_devices();
 209         dump_pci_device(PCI_DEV(0, 0x18, 2));
 210 #endif
 211 }