2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_MP_TABLE object mptable.o end
47 if HAVE_PIRQ_TABLE object irq_tables.o end
49 ## ATI Rage XL framebuffering graphics driver
50 dir /drivers/ati/ragexl
56 depends "$(MAINBOARD)/failover.c ./romcc"
57 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
60 makerule ./failover.inc
61 depends "$(MAINBOARD)/failover.c ./romcc"
62 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
66 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
67 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
70 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
71 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
75 ## Build our 16 bit and 32 bit linuxBIOS entry code
77 mainboardinit cpu/x86/16bit/entry16.inc
78 mainboardinit cpu/x86/32bit/entry32.inc
79 ldscript /cpu/x86/16bit/entry16.lds
80 ldscript /cpu/x86/32bit/entry32.lds
83 ## Build our reset vector (This is where linuxBIOS is entered)
86 mainboardinit cpu/x86/16bit/reset16.inc
87 ldscript /cpu/x86/16bit/reset16.lds
89 mainboardinit cpu/x86/32bit/reset32.inc
90 ldscript /cpu/x86/32bit/reset32.lds
93 ### Should this be in the northbridge code?
94 mainboardinit arch/i386/lib/cpu_reset.inc
97 ## Include an id string (For safe flashing)
99 mainboardinit arch/i386/lib/id.inc
100 ldscript /arch/i386/lib/id.lds
103 ### This is the early phase of linuxBIOS startup
104 ### Things are delicate and we test to see if we should
105 ### failover to another image.
107 if USE_FALLBACK_IMAGE
108 ldscript /arch/i386/lib/failover.lds
109 mainboardinit ./failover.inc
113 ### O.k. We aren't just an intermediary anymore!
119 mainboardinit cpu/x86/fpu/enable_fpu.inc
120 mainboardinit cpu/x86/mmx/enable_mmx.inc
121 mainboardinit cpu/x86/sse/enable_sse.inc
122 mainboardinit ./auto.inc
123 mainboardinit cpu/x86/sse/disable_sse.inc
124 mainboardinit cpu/x86/mmx/disable_mmx.inc
127 ## Include the secondary Configuration files
132 # config for arima/hdama
133 chip northbridge/amd/amdk8
134 device pci_domain 0 on
135 device pci 18.0 on # LDT 0
136 chip southbridge/amd/amd8131
137 device pci 0.0 on end
138 device pci 0.1 on end
139 device pci 1.0 on end
140 device pci 1.1 on end
142 chip southbridge/amd/amd8111
143 # this "device pci 0.0" is the parent the next one
146 device pci 0.0 on end
147 device pci 0.1 on end
148 device pci 0.2 on end
149 device pci 1.0 off end
152 chip superio/winbond/w83627hf
153 device pnp 2e.0 on # Floppy
158 device pnp 2e.1 off # Parallel Port
162 device pnp 2e.2 on # Com1
166 device pnp 2e.3 off # Com2
170 device pnp 2e.5 on # Keyboard
176 device pnp 2e.6 off end # CIR
177 device pnp 2e.7 off end # GAME_MIDI_GIPO1
178 device pnp 2e.8 off end # GPIO2
179 device pnp 2e.9 off end # GPIO3
180 device pnp 2e.a off end # ACPI
181 device pnp 2e.b on # HW Monitor
184 register "com1" = "{1}"
185 # register "com1" = "{1, 0, 0x3f8, 4}"
186 # register "lpt" = "{1}"
189 device pci 1.1 on end
190 device pci 1.2 on end
191 device pci 1.3 on end
192 device pci 1.5 off end
193 device pci 1.6 off end
196 device pci 18.0 on end # LDT1
197 device pci 18.0 on end # LDT2
198 device pci 18.1 on end
199 device pci 18.2 on end
200 device pci 18.3 on end
202 chip northbridge/amd/amdk8
203 device pci 19.0 on end
204 device pci 19.0 on end
205 device pci 19.0 on end
206 device pci 19.1 on end
207 device pci 19.2 on end
208 device pci 19.3 on end
211 device apic_cluster 0 on
212 chip cpu/amd/socket_940
215 chip cpu/amd/socket_940