Fill out ChromeOS specific coreboot table extensions
[coreboot.git] / src / lib / generic_sdram.c
1 #include <lib.h> /* Prototypes */
2
3 static inline void print_debug_sdram_8(const char *strval, uint32_t val)
4 {
5 #if CONFIG_CACHE_AS_RAM
6         printk(BIOS_DEBUG, "%s%02x\n", strval, val);
7 #else
8         print_debug(strval); print_debug_hex8(val); print_debug("\n");
9 #endif
10 }
11
12 /* Setup SDRAM */
13 #if CONFIG_RAMINIT_SYSINFO
14 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo)
15 #else
16 void sdram_initialize(int controllers, const struct mem_controller *ctrl)
17 #endif
18 {
19         int i;
20         /* Set the registers we can set once to reasonable values */
21         for(i = 0; i < controllers; i++) {
22                 print_debug_sdram_8("Ram1.", i);
23
24         #if CONFIG_RAMINIT_SYSINFO
25                 sdram_set_registers(ctrl + i, sysinfo);
26         #else
27                 sdram_set_registers(ctrl + i);
28         #endif
29         }
30
31         /* Now setup those things we can auto detect */
32         for(i = 0; i < controllers; i++) {
33                 print_debug_sdram_8("Ram2.", i);
34
35         #if CONFIG_RAMINIT_SYSINFO
36                 sdram_set_spd_registers(ctrl + i, sysinfo);
37         #else
38                 sdram_set_spd_registers(ctrl + i);
39         #endif
40
41         }
42
43         /* Now that everything is setup enable the SDRAM.
44          * Some chipsets do the work for us while on others
45          * we need to it by hand.
46          */
47         print_debug("Ram3\n");
48
49         #if CONFIG_RAMINIT_SYSINFO
50         sdram_enable(controllers, ctrl, sysinfo);
51         #else
52         sdram_enable(controllers, ctrl);
53         #endif
54
55         print_debug("Ram4\n");
56 }