2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Eric Biederman
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
31 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
32 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
33 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
34 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
37 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
38 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
40 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
41 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
42 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
43 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
46 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
47 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
48 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
49 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
50 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
51 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
52 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
53 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
54 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
56 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
57 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
60 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
61 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
62 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
63 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
64 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
65 #define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
66 #define UART_LCR_PEN 0x08 /* Parity eneble */
67 #define UART_LCR_EPS 0x10 /* Even Parity Select */
68 #define UART_LCR_STKP 0x20 /* Stick Parity */
69 #define UART_LCR_SBRK 0x40 /* Set Break */
70 #define UART_LCR_BKSE 0x80 /* Bank select enable */
71 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
74 #define UART_MCR_DTR 0x01 /* DTR */
75 #define UART_MCR_RTS 0x02 /* RTS */
76 #define UART_MCR_OUT1 0x04 /* Out 1 */
77 #define UART_MCR_OUT2 0x08 /* Out 2 */
78 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
80 #define UART_MCR_DMA_EN 0x04
81 #define UART_MCR_TX_DFR 0x08
88 #define UART_LSR_DR 0x01 /* Data ready */
89 #define UART_LSR_OE 0x02 /* Overrun */
90 #define UART_LSR_PE 0x04 /* Parity error */
91 #define UART_LSR_FE 0x08 /* Framing error */
92 #define UART_LSR_BI 0x10 /* Break */
93 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
94 #define UART_LSR_TEMT 0x40 /* Xmitter empty */
95 #define UART_LSR_ERR 0x80 /* Error */
98 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
99 #define UART_MSR_RI 0x40 /* Ring Indicator */
100 #define UART_MSR_DSR 0x20 /* Data Set Ready */
101 #define UART_MSR_CTS 0x10 /* Clear to Send */
102 #define UART_MSR_DDCD 0x08 /* Delta DCD */
103 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
104 #define UART_MSR_DDSR 0x02 /* Delta DSR */
105 #define UART_MSR_DCTS 0x01 /* Delta CTS */
107 #define UART_SCR 0x07
108 #define UART_SPR 0x07
110 #if ((115200 % CONFIG_TTYS0_BAUD) != 0)
111 #error Bad ttyS0 baud rate
114 /* Line Control Settings */
115 #define UART_LCS CONFIG_TTYS0_LCS
118 unsigned char uart8250_rx_byte(unsigned base_port);
119 int uart8250_can_rx_byte(unsigned base_port);
120 void uart8250_tx_byte(unsigned base_port, unsigned char data);
121 void uart8250_tx_flush(unsigned base_port);
123 /* Yes it is silly to have three different uart init functions. But we used to
124 * have three different sets of uart code, so it's an improvement.
126 void uart8250_init(unsigned base_port, unsigned divisor);
127 void uart_init(void);
129 /* and the same for memory mapped uarts */
130 unsigned char uart8250_mem_rx_byte(unsigned base_port);
131 int uart8250_mem_can_rx_byte(unsigned base_port);
132 void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
133 void uart8250_mem_tx_flush(unsigned base_port);
134 void uart8250_mem_init(unsigned base_port, unsigned divisor);
135 u32 uart_mem_init(void);
136 u32 uartmem_getbaseaddr(void);
138 #if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \
139 CONFIG_CONSOLE_SERIAL8250MEM
140 /* and special init for OXPCIe based cards */
141 extern int oxford_oxpcie_present;
143 void oxford_init(void);
146 #endif /* __ROMCC__ */
148 #endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
150 #endif /* UART8250_H */