2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Eric Biederman
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #ifndef CONFIG_TTYS0_BASE
25 #define CONFIG_TTYS0_BASE 0x3f8
28 #ifndef CONFIG_TTYS0_BAUD
29 #define CONFIG_TTYS0_BAUD 115200
31 #if ((115200%CONFIG_TTYS0_BAUD) != 0)
32 #error Bad ttys0 baud rate
35 /* Line Control Settings */
36 #ifndef CONFIG_TTYS0_LCS
37 /* Set 8bit, 1 stop bit, no parity */
38 #define CONFIG_TTYS0_LCS 0x3
41 #define UART_LCS CONFIG_TTYS0_LCS
50 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
51 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
52 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
53 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
56 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
57 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
59 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
60 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
61 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
62 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
65 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
66 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
67 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
68 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
69 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
70 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
71 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
72 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
73 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
75 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
76 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
79 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
80 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
81 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
82 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
83 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
84 #define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
85 #define UART_LCR_PEN 0x08 /* Parity eneble */
86 #define UART_LCR_EPS 0x10 /* Even Parity Select */
87 #define UART_LCR_STKP 0x20 /* Stick Parity */
88 #define UART_LCR_SBRK 0x40 /* Set Break */
89 #define UART_LCR_BKSE 0x80 /* Bank select enable */
90 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
93 #define UART_MCR_DTR 0x01 /* DTR */
94 #define UART_MCR_RTS 0x02 /* RTS */
95 #define UART_MCR_OUT1 0x04 /* Out 1 */
96 #define UART_MCR_OUT2 0x08 /* Out 2 */
97 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
99 #define UART_MCR_DMA_EN 0x04
100 #define UART_MCR_TX_DFR 0x08
102 #define UART_DLL 0x00
103 #define UART_DLM 0x01
106 #define UART_LSR 0x05
107 #define UART_LSR_DR 0x01 /* Data ready */
108 #define UART_LSR_OE 0x02 /* Overrun */
109 #define UART_LSR_PE 0x04 /* Parity error */
110 #define UART_LSR_FE 0x08 /* Framing error */
111 #define UART_LSR_BI 0x10 /* Break */
112 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
113 #define UART_LSR_TEMT 0x40 /* Xmitter empty */
114 #define UART_LSR_ERR 0x80 /* Error */
116 #define UART_MSR 0x06
117 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
118 #define UART_MSR_RI 0x40 /* Ring Indicator */
119 #define UART_MSR_DSR 0x20 /* Data Set Ready */
120 #define UART_MSR_CTS 0x10 /* Clear to Send */
121 #define UART_MSR_DDCD 0x08 /* Delta DCD */
122 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
123 #define UART_MSR_DDSR 0x02 /* Delta DSR */
124 #define UART_MSR_DCTS 0x01 /* Delta CTS */
126 #define UART_SCR 0x07
127 #define UART_SPR 0x07
131 unsigned char uart8250_rx_byte(unsigned base_port);
132 int uart8250_can_rx_byte(unsigned base_port);
133 void uart8250_tx_byte(unsigned base_port, unsigned char data);
134 void uart8250_tx_flush(unsigned base_port);
136 /* Yes it is silly to have three different uart init functions. But we used to
137 * have three different sets of uart code, so it's an improvement.
139 void uart8250_init(unsigned base_port, unsigned divisor);
140 void uart_init(void);
142 /* and the same for memory mapped uarts */
143 unsigned char uart8250_mem_rx_byte(unsigned base_port);
144 int uart8250_mem_can_rx_byte(unsigned base_port);
145 void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
146 void uart8250_mem_tx_flush(unsigned base_port);
147 void uart8250_mem_init(unsigned base_port, unsigned divisor);
148 u32 uart_mem_init(void);
149 u32 uartmem_getbaseaddr(void);
151 /* and special init for OXPCIe based cards */
152 void oxford_init(void);
156 #endif /* UART8250_H */