3 #include <device/path.h>
5 /* chips are arbitrary chips (superio, southbridge, etc.)
6 * They have private structures that define chip resources and default
7 * settings. They have four externally visible functions for control.
8 * They have a generic component which applies to all chips for
12 /* some of the types of resources chips can control */
13 #if CONFIG_CHIP_CONFIGURE == 1
14 #define CONFIGURE(pass) chip_configure(&static_root, pass)
16 #define CONFIGURE(pass)
20 unsigned int enable,baud, base, irq;
23 /* lpt port description.
24 * Note that for many chips you only really need to define the
28 unsigned int enable, // 1 if this port is enabled
30 base, // IO base of the parallel port
35 CONF_PASS_PRE_CONSOLE,
37 CONF_PASS_PRE_DEVICE_ENUMERATE,
38 CONF_PASS_PRE_DEVICE_CONFIGURE,
39 CONF_PASS_PRE_DEVICE_ENABLE,
40 CONF_PASS_PRE_DEVICE_INITIALIZE,
46 /* linkages from devices of a type (e.g. superio devices)
47 * to the actual physical PCI device. This type is used in an array of
48 * structs built by NLBConfig.py. We owe this idea to Plan 9.
53 /* there is one of these for each TYPE of chip */
55 /* This is the print name for debugging */
57 void (*enable)(struct chip *, enum chip_pass);
58 void (*enumerate)(struct chip *chip);
62 struct chip_device_path {
63 struct device_path path;
71 #ifndef MAX_CHIP_PATHS
72 #define MAX_CHIP_PATHS 16
75 struct chip_control *control; /* for this device */
76 struct chip_device_path path[MAX_CHIP_PATHS]; /* can be 0, in which case the default is taken */
77 char *configuration; /* can be 0. */
78 struct chip *next, *children;
79 /* there is one of these for each INSTANCE of a chip */
80 void *chip_info; /* the dreaded "void *" */
81 /* bus and device links into the device tree */
86 extern struct chip static_root;
87 extern void chip_configure(struct chip *, enum chip_pass);
88 extern void chip_enumerate(struct chip *chip);
89 #endif /* DEVICE_CHIP_H */