1 /* chips are arbitrary chips (superio, southbridge, etc.)
2 * They have private structures that define chip resources and default
3 * settings. They have four externally visible functions for control.
4 * new settings are provided as ascii strings.
7 /* some of the types of resources chips can control */
10 unsigned int enable,baud, base, irq;
13 /* lpt port description.
14 * Note that for many chips you only really need to define the
18 unsigned int enable, // 1 if this port is enabled
20 base, // IO base of the parallel port
26 /* linkages from devices of a type (e.g. superio devices)
27 * to the actual physical PCI device. This type is used in an array of
28 * structs built by NLBConfig.py. We owe this idea to Plan 9.
34 void (*alloc)(struct chip *s);
35 void (*pre_pci_init)(struct chip *s);
36 void (*init)(struct chip *s);
37 void (*finishup)(struct chip *s);
38 char *path; /* the default path. Can be overridden
39 * by commands in config
41 // This is the print name for debugging
46 struct chip_control *control; /* for this device */
47 char *path; /* can be 0, in which case the default is taken */
48 char *configuration; /* can be 0. */