1 /* chips are arbitrary chips (superio, southbridge, etc.)
2 * They have private structures that define chip resources and default
3 * settings. They have four externally visible functions for control.
4 * They have a generic component which applies to all chips for
8 /* some of the types of resources chips can control */
9 #ifndef CONFIG_CHIP_CONFIGURE
10 #define CONFIGURE(pass) chip_configure(&static_root, pass)
12 #define CONFIGURE(pass)
16 unsigned int enable,baud, base, irq;
19 /* lpt port description.
20 * Note that for many chips you only really need to define the
24 unsigned int enable, // 1 if this port is enabled
26 base, // IO base of the parallel port
31 CONF_PASS_PRE_CONSOLE,
33 CONF_PASS_PRE_DEVICE_ENUMERATE,
34 CONF_PASS_PRE_DEVICE_CONFIGURE,
35 CONF_PASS_PRE_DEVICE_ENABLE,
36 CONF_PASS_PRE_DEVICE_INITIALIZE,
42 /* linkages from devices of a type (e.g. superio devices)
43 * to the actual physical PCI device. This type is used in an array of
44 * structs built by NLBConfig.py. We owe this idea to Plan 9.
49 /* there is one of these for each TYPE of chip */
51 void (*enable)(struct chip *, enum chip_pass);
52 char *path; /* the default path. Can be overridden
53 * by commands in config
55 // This is the print name for debugging
60 struct chip_control *control; /* for this device */
61 char *path; /* can be 0, in which case the default is taken */
62 char *configuration; /* can be 0. */
64 struct chip *next, *children;
65 /* there is one of these for each INSTANCE of a chip */
66 void *chip_info; /* the dreaded "void *" */
69 extern struct chip static_root;
70 extern void chip_configure(struct chip *, enum chip_pass);