src/include/cpu/x86/smm.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* AMD64 SMM State-Save Area
  21  * starts @ 0x7e00
  22  */
  23
  24 #ifndef CPU_X86_SMM_H
  25 #define CPU_X86_SMM_H
  26
  27 #include <types.h>
  28 typedef struct {
  29         u16     es_selector;
  30         u16     es_attributes;
  31         u32     es_limit;
  32         u64     es_base;
  33
  34         u16     cs_selector;
  35         u16     cs_attributcs;
  36         u32     cs_limit;
  37         u64     cs_base;
  38
  39         u16     ss_selector;
  40         u16     ss_attributss;
  41         u32     ss_limit;
  42         u64     ss_base;
  43
  44         u16     ds_selector;
  45         u16     ds_attributds;
  46         u32     ds_limit;
  47         u64     ds_base;
  48
  49         u16     fs_selector;
  50         u16     fs_attributfs;
  51         u32     fs_limit;
  52         u64     fs_base;
  53
  54         u16     gs_selector;
  55         u16     gs_attributgs;
  56         u32     gs_limit;
  57         u64     gs_base;
  58
  59         u8      reserved0[4];
  60         u16     gdtr_limit;
  61         u8      reserved1[2];
  62         u64     gdtr_base;
  63
  64         u16     ldtr_selector;
  65         u16     ldtr_attributes;
  66         u32     ldtr_limit;
  67         u64     ldtr_base;
  68
  69         u8      reserved2[4];
  70         u16     idtr_limit;
  71         u8      reserved3[2];
  72         u64     idtr_base;
  73
  74         u16     tr_selector;
  75         u16     tr_attributes;
  76         u32     tr_limit;
  77         u64     tr_base;
  78
  79         u8      reserved4[40];
  80
  81         u8      io_restart;
  82         u8      autohalt_restart;
  83
  84         u8      reserved5[6];
  85
  86         u64     efer;
  87
  88         u8      reserved6[36];
  89
  90         u32     smm_revision;
  91         u32     smbase;
  92
  93         u8      reserved7[68];
  94
  95         u64     cr4;
  96         u64     cr3;
  97         u64     cr0;
  98         u64     dr7;
  99         u64     dr6;
 100
 101         u64     rflags;
 102         u64     rip;
 103         u64     r15;
 104         u64     r14;
 105         u64     r13;
 106         u64     r12;
 107         u64     r11;
 108         u64     r10;
 109         u64     r9;
 110         u64     r8;
 111
 112         u64     rdi;
 113         u64     rsi;
 114         u64     rpb;
 115         u64     rsp;
 116         u64     rbx;
 117         u64     rdx;
 118         u64     rcx;
 119         u64     rax;
 120 } __attribute__((packed)) amd64_smm_state_save_area_t;
 121
 122
 123 /* Intel Core 2 (EM64T) SMM State-Save Area
 124  * starts @ 0x7d00
 125  */
 126 typedef struct {
 127         u8      reserved0[208];
 128
 129         u32     gdtr_upper_base;
 130         u32     ldtr_upper_base;
 131         u32     idtr_upper_base;
 132
 133         u8      reserved1[4];
 134
 135         u64     io_rdi;
 136         u64     io_rip;
 137         u64     io_rcx;
 138         u64     io_rsi;
 139         u64     cr4;
 140
 141         u8      reserved2[68];
 142
 143         u64     gdtr_base;
 144         u64     idtr_base;
 145         u64     ldtr_base;
 146
 147         u8      reserved3[84];
 148
 149         u32     smm_revision;
 150         u32     smbase;
 151
 152         u16     io_restart;
 153         u16     autohalt_restart;
 154
 155         u8      reserved4[24];
 156
 157         u64     r15;
 158         u64     r14;
 159         u64     r13;
 160         u64     r12;
 161         u64     r11;
 162         u64     r10;
 163         u64     r9;
 164         u64     r8;
 165
 166         u64     rax;
 167         u64     rcx;
 168         u64     rdx;
 169         u64     rbx;
 170
 171         u64     rsp;
 172         u64     rbp;
 173         u64     rsi;
 174         u64     rdi;
 175
 176
 177         u64     io_mem_addr;
 178         u32     io_misc_info;
 179
 180         u32     es_sel;
 181         u32     cs_sel;
 182         u32     ss_sel;
 183         u32     ds_sel;
 184         u32     fs_sel;
 185         u32     gs_sel;
 186
 187         u32     ldtr_sel;
 188         u32     tr_sel;
 189
 190         u64     dr7;
 191         u64     dr6;
 192         u64     rip;
 193         u64     efer;
 194         u64     rflags;
 195
 196         u64     cr3;
 197         u64     cr0;
 198 } __attribute__((packed)) em64t_smm_state_save_area_t;
 199
 200
 201 /* Legacy x86 SMM State-Save Area
 202  * starts @ 0x7e00
 203  */
 204
 205 typedef struct {
 206         u8      reserved0[248];
 207         u32     smbase;
 208         u32     smm_revision;
 209         u16     io_restart;
 210         u16     autohalt_restart;
 211         u8      reserved1[132];
 212         u32     gdtbase;
 213         u8      reserved2[8];
 214         u32     idtbase;
 215         u8      reserved3[16];
 216         u32     es;
 217         u32     cs;
 218         u32     ss;
 219         u32     ds;
 220         u32     fs;
 221         u32     gs;
 222         u32     ldtbase;
 223         u32     tr;
 224         u32     dr7;
 225         u32     dr6;
 226         u32     eax;
 227         u32     ecx;
 228         u32     edx;
 229         u32     ebx;
 230         u32     esp;
 231         u32     ebp;
 232         u32     esi;
 233         u32     edi;
 234         u32     eip;
 235         u32     eflags;
 236         u32     cr3;
 237         u32     cr0;
 238 } __attribute__((packed)) legacy_smm_state_save_area_t;
 239
 240 typedef enum {
 241         AMD64,
 242         EM64T,
 243         LEGACY
 244 } save_state_type_t;
 245
 246
 247 typedef struct {
 248         save_state_type_t type;
 249         union {
 250         amd64_smm_state_save_area_t *amd64_state_save;
 251         em64t_smm_state_save_area_t *em64t_state_save;
 252         legacy_smm_state_save_area_t *legacy_state_save;
 253         };
 254 } smm_state_save_area_t;
 255
 256 #define APM_CNT         0xb2
 257 #define APM_CNT_CST_CONTROL     0x85
 258 #define APM_CNT_PST_CONTROL     0x80
 259 #define APM_CNT_ACPI_DISABLE    0x1e
 260 #define APM_CNT_ACPI_ENABLE     0xe1
 261 #define APM_CNT_MBI_UPDATE      0xeb
 262 #define APM_CNT_GNVS_UPDATE     0xea
 263 #define APM_STS         0xb3
 264
 265 /* SMI handler function prototypes */
 266 void smi_handler(u32 smm_revision);
 267
 268 void io_trap_handler(int smif);
 269 int southbridge_io_trap_handler(int smif);
 270 int __attribute__((weak)) mainboard_io_trap_handler(int smif);
 271
 272 void southbridge_smi_set_eos(void);
 273
 274 void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 275 void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 276 void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 277
 278 void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
 279 int __attribute__((weak)) mainboard_apm_cnt(u8 data);
 280 void smi_release_lock(void);
 281
 282 #endif