src/include/cpu/p6/apic.h

   1 #ifndef APIC_H
   2 #define APIC_H
   3
   4 #define APIC_BASE_MSR 0x1B
   5 #define APIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8)
   6 #define APIC_BASE_MSR_ENABLE (1 << 11)
   7 #define APIC_BASE_MSR_ADDR_MASK 0xFFFFF000
   8
   9 #define APIC_DEFAULT_BASE 0xfee00000
  10
  11 #define APIC_ID         0x020
  12 #define APIC_LVR        0x030
  13 #define APIC_TASKPRI    0x80
  14 #define         APIC_TPRI_MASK          0xFF
  15 #define APIC_ARBID      0x090
  16 #define APIC_RRR        0x0C0
  17 #define APIC_SVR        0x0f0
  18 #define APIC_SPIV       0x0f0
  19 #define         APIC_SPIV_ENABLE  0x100
  20 #define APIC_ESR        0x280
  21 #define         APIC_ESR_SEND_CS        0x00001
  22 #define         APIC_ESR_RECV_CS        0x00002
  23 #define         APIC_ESR_SEND_ACC       0x00004
  24 #define         APIC_ESR_RECV_ACC       0x00008
  25 #define         APIC_ESR_SENDILL        0x00020
  26 #define         APIC_ESR_RECVILL        0x00040
  27 #define         APIC_ESR_ILLREGA        0x00080
  28 #define APIC_ICR        0x300
  29 #define         APIC_DEST_SELF          0x40000
  30 #define         APIC_DEST_ALLINC        0x80000
  31 #define         APIC_DEST_ALLBUT        0xC0000
  32 #define         APIC_ICR_RR_MASK        0x30000
  33 #define         APIC_ICR_RR_INVALID     0x00000
  34 #define         APIC_ICR_RR_INPROG      0x10000
  35 #define         APIC_ICR_RR_VALID       0x20000
  36 #define         APIC_INT_LEVELTRIG      0x08000
  37 #define         APIC_INT_ASSERT         0x04000
  38 #define         APIC_ICR_BUSY           0x01000
  39 #define         APIC_DEST_LOGICAL       0x00800
  40 #define         APIC_DM_FIXED           0x00000
  41 #define         APIC_DM_LOWEST          0x00100
  42 #define         APIC_DM_SMI             0x00200
  43 #define         APIC_DM_REMRD           0x00300
  44 #define         APIC_DM_NMI             0x00400
  45 #define         APIC_DM_INIT            0x00500
  46 #define         APIC_DM_STARTUP         0x00600
  47 #define         APIC_DM_EXTINT          0x00700
  48 #define         APIC_VECTOR_MASK        0x000FF
  49 #define APIC_ICR2       0x310
  50 #define         GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  51 #define         SET_APIC_DEST_FIELD(x)  ((x)<<24)
  52 #define APIC_LVTT       0x320
  53 #define APIC_LVTPC      0x340
  54 #define APIC_LVT0       0x350
  55 #define         APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  56 #define         GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  57 #define         SET_APIC_TIMER_BASE(x)          (((x)<<18))
  58 #define         APIC_TIMER_BASE_CLKIN           0x0
  59 #define         APIC_TIMER_BASE_TMBASE          0x1
  60 #define         APIC_TIMER_BASE_DIV             0x2
  61 #define         APIC_LVT_TIMER_PERIODIC         (1<<17)
  62 #define         APIC_LVT_MASKED                 (1<<16)
  63 #define         APIC_LVT_LEVEL_TRIGGER          (1<<15)
  64 #define         APIC_LVT_REMOTE_IRR             (1<<14)
  65 #define         APIC_INPUT_POLARITY             (1<<13)
  66 #define         APIC_SEND_PENDING               (1<<12)
  67 #define         APIC_LVT_RESERVED_1             (1<<11)
  68 #define         APIC_DELIVERY_MODE_MASK         (7<<8)
  69 #define         APIC_DELIVERY_MODE_FIXED        (0<<8)
  70 #define         APIC_DELIVERY_MODE_NMI          (4<<8)
  71 #define         APIC_DELIVERY_MODE_EXTINT       (7<<8)
  72 #define         GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  73 #define         SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  74 #define                 APIC_MODE_FIXED         0x0
  75 #define                 APIC_MODE_NMI           0x4
  76 #define                 APIC_MODE_EXINT         0x7
  77 #define APIC_LVT1       0x360
  78 #define APIC_LVTERR     0x370
  79 #define APIC_TMICT      0x380
  80 #define APIC_TMCCT      0x390
  81 #define APIC_TDCR       0x3E0
  82 #define         APIC_TDR_DIV_TMBASE     (1<<2)
  83 #define         APIC_TDR_DIV_1          0xB
  84 #define         APIC_TDR_DIV_2          0x0
  85 #define         APIC_TDR_DIV_4          0x1
  86 #define         APIC_TDR_DIV_8          0x2
  87 #define         APIC_TDR_DIV_16         0x3
  88 #define         APIC_TDR_DIV_32         0x8
  89 #define         APIC_TDR_DIV_64         0x9
  90 #define         APIC_TDR_DIV_128        0xA
  91
  92 #if defined(__ROMCC__) || !defined(ASSEMBLY)
  93
  94 static inline unsigned long apic_read(unsigned long reg)
  95 {
  96         return *((volatile unsigned long *)(APIC_DEFAULT_BASE+reg));
  97 }
  98
  99 static inline void apic_write(unsigned long reg, unsigned long v)
 100 {
 101         *((volatile unsigned long *)(APIC_DEFAULT_BASE+reg)) = v;
 102 }
 103
 104 static inline void apic_wait_icr_idle(void)
 105 {
 106         do { } while ( apic_read( APIC_ICR ) & APIC_ICR_BUSY );
 107 }
 108
 109
 110 #endif
 111
 112 #if !defined(ASSEMBLY)
 113
 114 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 115
 116 struct __xchg_dummy { unsigned long a[100]; };
 117 #define __xg(x) ((struct __xchg_dummy *)(x))
 118
 119 /*
 120  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
 121  * Note 2: xchg has side effect, so that attribute volatile is necessary,
 122  *        but generally the primitive is invalid, *ptr is output argument. --ANK
 123  */
 124 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 125 {
 126         switch (size) {
 127                 case 1:
 128                         __asm__ __volatile__("xchgb %b0,%1"
 129                                 :"=q" (x)
 130                                 :"m" (*__xg(ptr)), "0" (x)
 131                                 :"memory");
 132                         break;
 133                 case 2:
 134                         __asm__ __volatile__("xchgw %w0,%1"
 135                                 :"=r" (x)
 136                                 :"m" (*__xg(ptr)), "0" (x)
 137                                 :"memory");
 138                         break;
 139                 case 4:
 140                         __asm__ __volatile__("xchgl %0,%1"
 141                                 :"=r" (x)
 142                                 :"m" (*__xg(ptr)), "0" (x)
 143                                 :"memory");
 144                         break;
 145         }
 146         return x;
 147 }
 148
 149
 150 extern inline void apic_write_atomic(unsigned long reg, unsigned long v)
 151 {
 152         xchg((volatile unsigned long *)(APIC_DEFAULT_BASE+reg), v);
 153 }
 154
 155
 156 #ifdef CONFIG_X86_GOOD_APIC
 157 # define FORCE_READ_AROUND_WRITE 0
 158 # define apic_read_around(x) apic_read(x)
 159 # define apic_write_around(x,y) apic_write((x),(y))
 160 #else
 161 # define FORCE_READ_AROUND_WRITE 1
 162 # define apic_read_around(x) apic_read(x)
 163 # define apic_write_around(x,y) apic_write_atomic((x),(y))
 164 #endif
 165
 166 static inline int apic_remote_read(int apicid, int reg, unsigned long *pvalue)
 167 {
 168         int timeout;
 169         unsigned long status;
 170         int result;
 171         apic_wait_icr_idle();
 172         apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 173         apic_write_around(APIC_ICR, APIC_DM_REMRD | (reg >> 4));
 174         timeout = 0;
 175         do {
 176 #if 0
 177                 udelay(100);
 178 #endif
 179                 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
 180         } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
 181
 182         result = -1;
 183         if (status == APIC_ICR_RR_VALID) {
 184                 *pvalue = apic_read(APIC_RRR);
 185                 result = 0;
 186         }
 187         return result;
 188 }
 189 #endif /* ASSEMBLY */
 190
 191 #endif /* APIC_H */