2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 /* MWAIT coordination I/O base address. This must match
23 * the \_PR_.CPU0 PM base address.
25 #define PMB0_BASE 0x510
27 /* PMB1: I/O port that triggers SMI once cores are in the same state.
28 * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
30 #define PMB1_BASE 0x800