4 #define IORR_FIRST 0xC0010016
5 #define IORR_LAST 0xC0010019
7 #define MTRR_READ_MEM (1 << 4)
8 #define MTRR_WRITE_MEM (1 << 3)
10 #define SYSCFG_MSR 0xC0010010
11 #define SYSCFG_MSR_TOM2En (1 << 21)
12 #define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
13 #define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
14 #define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
15 #define SYSCFG_MSR_UcLockEn (1 << 17)
16 #define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
17 #define SYSCFG_MSR_ClVicBlkEn (1 << 11)
18 #define SYSCFG_MSR_SetDirtyEnO (1 << 10)
19 #define SYSCFG_MSR_SetDirtyEnS (1 << 9)
20 #define SYSCFG_MSR_SetDirtyEnE (1 << 8)
21 #define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
22 #define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
24 #define IORR0_BASE 0xC0010016
25 #define IORR0_MASK 0xC0010017
26 #define IORR1_BASE 0xC0010018
27 #define IORR1_MASK 0xC0010019
28 #define TOP_MEM 0xC001001A
29 #define TOP_MEM2 0xC001001D
31 #define TOP_MEM_MASK 0x007fffff
32 #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
35 void amd_setup_mtrrs(void);
36 #endif /* __ROMCC__ */
38 #endif /* CPU_AMD_MTRR_H */