2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
5 * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2006 Stefan Reinauer <stepan@coresystems.de>
7 * Copyright (C) 2006 Andrei Birjukov <andrei.birjukov@artecdesign.ee>
8 * Copyright (C) 2007 Advanced Micro Devices, Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #ifndef CPU_AMD_LXDEF_H
26 #define CPU_AMD_LXDEF_H
27 #define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/
28 #define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/
29 #define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/
30 #define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/
32 #define CPU_REV_1_0 0x011
33 #define CPU_REV_1_1 0x012
34 #define CPU_REV_1_2 0x013
35 #define CPU_REV_1_3 0x014
36 #define CPU_REV_2_0 0x020
37 #define CPU_REV_2_1 0x021
38 #define CPU_REV_2_2 0x022
39 #define CPU_REV_3_0 0x030
40 /* GeodeLink Control Processor Registers, GLIU1, Port 3 */
41 #define GLCP_CLK_DIS_DELAY 0x4c000008
42 #define GLCP_PMCLKDISABLE 0x4c000009
43 #define GLCP_CHIP_REVID 0x4c000017
45 /* GLCP_SYS_RSTPLL, Upper 32 bits */
46 #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
47 #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
48 #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
50 /* GLCP_SYS_RSTPLL, Lower 32 bits */
51 #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
52 #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
54 #define GLCP_SYS_RSTPLL_LOCKWAIT 24
55 #define GLCP_SYS_RSTPLL_HOLDCOUNT 16
56 #define GLCP_SYS_RSTPLL_BYPASS 15
57 #define GLCP_SYS_RSTPLL_PD 14
58 #define GLCP_SYS_RSTPLL_RESETPLL 13
59 #define GLCP_SYS_RSTPLL_DDRMODE 10
60 #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
61 #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
62 #define GLCP_SYS_RSTPLL_CHIP_RESET 0
64 /* MSR routing as follows*/
65 /* MSB = 1 means not for CPU*/
66 /* next 3 bits 1st port*/
67 /* next3 bits next port if through an GLIU*/
70 /*Redcloud as follows.*/
87 /* start GX3 def, differences are marked with GX3 comment */
95 //#define GL0_DF 6 //GX3 no such thing as VP port
105 #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
106 #define MSR_MC (GL0_MC << 29) /* 2000xxxx */
107 #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
108 #define MSR_CPU (GL0_CPU << 32) /* 0000xxxx - this is not used for BIOS */ //GX3
109 #define MSR_VG (GL0_VG << 29) /* 8000xxxx */
110 #define MSR_GP (GL0_GP << 29) /* A000xxxx */
111 //#define MSR_DF (GL0_DF << 29) /* C000xxxx */ //GX3 no such thing
113 #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
114 #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
115 //#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ //GX3: no such thing
116 #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
117 #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
119 #define SB_PORT 2 /* port of the SouthBridge */
120 #define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* 5100xxxx - address to the SouthBridge*/
121 #define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/
125 /*GeodeLink Interface Unit 0 (GLIU0) port0*/
128 #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
129 #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
131 #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20)
132 #define GLIU0_CAP (MSR_GLIU0 + 0x86)
133 #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
137 /* Memory Controller GLIU0 port 1*/
139 #define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
140 #define MC_GLD_MSR_PM (MSR_MC + 0x2004)
142 #define MC_CF07_DATA (MSR_MC + 0x18)
144 #define CF07_UPPER_D1_SZ_SHIFT 28
145 #define CF07_UPPER_D1_MB_SHIFT 24
146 #define CF07_UPPER_D1_CB_SHIFT 20
147 #define CF07_UPPER_D1_PSZ_SHIFT 16
148 #define CF07_UPPER_D0_SZ_SHIFT 12
149 #define CF07_UPPER_D0_MB_SHIFT 8
150 #define CF07_UPPER_D0_CB_SHIFT 4
151 #define CF07_UPPER_D0_PSZ_SHIFT 0
153 #define CF07_LOWER_REF_INT_SHIFT 8
154 #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
155 #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
156 #define CF07_LOWER_EMR_QFC_SET (1 << 26)
157 #define CF07_LOWER_EMR_DRV_SET (1 << 25)
158 #define CF07_LOWER_REF_TEST_SET (1 << 3)
159 #define CF07_LOWER_PROG_DRAM_SET (1 << 0)
162 #define MC_CF8F_DATA (MSR_MC + 0x19)
164 #define CF8F_UPPER_XOR_BS_SHIFT 19
165 #define CF8F_UPPER_XOR_MB0_SHIFT 18
166 #define CF8F_UPPER_XOR_BA1_SHIFT 17
167 #define CF8F_UPPER_XOR_BA0_SHIFT 16
168 #define CF8F_UPPER_REORDER_DIS_SET (1 << 8)
169 #define CF8F_UPPER_REG_DIMM_SHIFT 4
170 #define CF8F_LOWER_CAS_LAT_SHIFT 28
171 #define CF8F_LOWER_REF2ACT_SHIFT 24
172 #define CF8F_LOWER_ACT2PRE_SHIFT 20
173 #define CF8F_LOWER_PRE2ACT_SHIFT 16
174 #define CF8F_LOWER_ACT2CMD_SHIFT 12
175 #define CF8F_LOWER_ACT2ACT_SHIFT 8
176 #define CF8F_UPPER_32BIT_SET (1 << 5)
177 #define CF8F_UPPER_HOI_LOI_SET (1 << 1)
179 #define MC_CF1017_DATA (MSR_MC + 0x1A)
181 #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
182 #define CF1017_LOWER_WR2DAT_SHIFT 0
184 #define MC_CFCLK_DBUG (MSR_MC + 0x1D)
186 #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
187 #define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1)
188 #define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
190 #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
191 #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
192 #define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
194 #define MC_CF_RDSYNC (MSR_MC + 0x1F)
198 /* GLIU1 GLIU0 port2*/
200 #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
201 #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
203 #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
207 /* CPU ; does not need routing instructions since we are executing there.*/
209 #define CPU_GLD_MSR_CAP 0x2000
210 #define CPU_GLD_MSR_CONFIG 0x2001
211 #define CPU_GLD_MSR_PM 0x2004
213 #define CPU_GLD_MSR_DIAG 0x2005
214 #define DIAG_SEL1_MODE_SHIFT 16
215 #define DIAG_SEL1_SET (1 << 31)
216 #define DIAG_SEL0__MODE_SHIFT 0
217 #define DIAG_SET0_SET (1 << 15)
219 #define CPU_PF_BTB_CONF 0x1100
220 #define BTB_ENABLE_SET (1 << 0)
221 #define RETURN_STACK_ENABLE_SET (1 << 4)
222 #define CPU_PF_BTBRMA_BIST 0x110C
224 #define CPU_XC_CONFIG 0x1210
225 #define XC_CONFIG_SUSP_ON_HLT (1 << 0)
226 #define CPU_ID_CONFIG 0x1250
227 #define ID_CONFIG_SERIAL_SET (1 << 0)
229 #define CPU_AC_MSR 0x1301
230 #define CPU_EX_BIST 0x1428
233 #define CPU_IM_CONFIG 0x1700
234 #define IM_CONFIG_LOWER_ICD_SET (1 << 8)
235 #define IM_CONFIG_LOWER_QWT_SET (1 << 20)
236 #define CPU_IC_INDEX 0x1710
237 #define CPU_IC_DATA 0x1711
238 #define CPU_IC_TAG 0x1712
239 #define CPU_IC_TAG_I 0x1713
240 #define CPU_ITB_INDEX 0x1720
241 #define CPU_ITB_LRU 0x1721
242 #define CPU_ITB_ENTRY 0x1722
243 #define CPU_ITB_ENTRY_I 0x1723
244 #define CPU_IM_BIST_TAG 0x1730
245 #define CPU_IM_BIST_DATA 0x1731
248 /* ----- GX3 OK ---- */
250 /* various CPU MSRs */
251 #define CPU_DM_CONFIG0 0x1800
252 #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
253 #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8)
254 #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
255 #define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
257 #define CPU_DM_CONFIG1 0x1801
259 #define CPU_DM_PFLOCK 0x1804
261 /* configuration MSRs */
262 #define CPU_RCONF_DEFAULT 0x1808
263 #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
264 #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4
265 #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0
266 #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28
267 #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
268 #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
271 #define CPU_RCONF_BYPASS 0x180A
272 #define CPU_RCONF_A0_BF 0x180B
273 #define CPU_RCONF_C0_DF 0x180C
274 #define CPU_RCONF_E0_FF 0x180D
276 /* ------------------------ */
278 /* ----- GX3 OK ---- */
280 #define CPU_RCONF_SMM 0x180E
281 #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
282 #define RCONF_SMM_UPPER_RCSMM_SHIFT 0
283 #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12
284 #define RCONF_SMM_LOWER_RCNORM_SHIFT 0
285 #define RCONF_SMM_LOWER_EN_SET (1<<8)
287 /* ------------------------ */
290 #define CPU_RCONF_DMM 0x180F
291 #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
292 #define RCONF_DMM_UPPER_RCDMM_SHIFT 0
293 #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12
294 #define RCONF_DMM_LOWER_RCNORM_SHIFT 0
295 #define RCONF_DMM_LOWER_EN_SET (1<<8)
299 /* ----- GX3 OK ---- */
301 #define CPU_RCONF0 0x1810
302 #define CPU_RCONF1 0x1811
303 #define CPU_RCONF2 0x1812
304 #define CPU_RCONF3 0x1813
305 #define CPU_RCONF4 0x1814
306 #define CPU_RCONF5 0x1815
307 #define CPU_RCONF6 0x1816
308 #define CPU_RCONF7 0x1817
310 /* ------------------------ */
312 /* ----- GX3 OK ---- */
314 #define CPU_CR1_MSR 0x1881
315 #define CPU_CR2_MSR 0x1882
316 #define CPU_CR3_MSR 0x1883
317 #define CPU_CR4_MSR 0x1884
319 /* ------------------------ */
321 /* ----- GX3 OK ---- */
323 #define CPU_DC_INDEX 0x1890
324 #define CPU_DC_DATA 0x1891
325 #define CPU_DC_TAG 0x1892
326 #define CPU_DC_TAG_I 0x1893
327 #define CPU_SNOOP 0x1894
328 #define CPU_DTB_INDEX 0x1898
329 #define CPU_DTB_LRU 0x1899
330 #define CPU_DTB_ENTRY 0x189A
331 #define CPU_DTB_ENTRY_I 0x189B
333 /* ------------------------ */
335 #define CPU_L2TB_INDEX 0x189C
336 #define CPU_L2TB_LRU 0x189D
337 #define CPU_L2TB_ENTRY 0x189E
338 #define CPU_L2TB_ENTRY_I 0x189F
339 #define CPU_DM_BIST 0x18C0
341 #define CPU_AC_SMM_CTL 0x1301
342 #define SMM_NMI_EN_SET (1<<0)
343 #define SMM_SUSP_EN_SET (1<<1)
344 #define NEST_SMI_EN_SET (1<<2)
345 #define SMM_INST_EN_SET (1<<3)
346 #define INTL_SMI_EN_SET (1<<4)
347 #define EXTL_SMI_EN_SET (1<<5)
349 #define CPU_FPU_MSR_MODE 0x1A00
350 #define FPU_IE_SET (1<<0)
352 #define CPU_FP_UROM_BIST 0x1A03
354 #define CPU_BC_CONF_0 0x1900
355 #define TSC_SUSP_SET (1<<5)
356 #define SUSP_EN_SET (1<<12)
360 #define L2_CONFIG_MSR 0x1920
361 #define L2_STATUS_MSR 0x1921
362 #define L2_BIST_MSR 0x1926
371 #define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
372 #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
373 #define VG_GLD_MSR_PM (MSR_VG + 0x2004)
375 #define GP_GLD_MSR_CAP (MSR_GP + 0x2000)
376 #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
377 #define GP_GLD_MSR_PM (MSR_GP + 0x2004)
385 #define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
386 #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
387 #define DF_LOWER_LCD_SHIFT 6
388 #define DF_GLD_MSR_PM (MSR_DF + 0x2004)
393 /* GeodeLink Control Processor GLIU1 port3*/
395 #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
396 #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
397 #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
399 #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
401 #define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W*/)
402 #define RSTPLL_UPPER_MDIV_SHIFT 9
403 #define RSTPLL_UPPER_VDIV_SHIFT 6
404 #define RSTPLL_UPPER_FBDIV_SHIFT 0
406 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26
407 #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
409 #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
410 #define RSTPPL_LOWER_BYPASS_SHIFT 15
411 #define RSTPPL_LOWER_TST_SHIFT 11
412 #define RSTPPL_LOWER_SDRMODE_SHIFT 10
413 #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
415 #define RSTPPL_LOWER_LOCK_SET (1<<25)
416 #define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
417 #define RSTPPL_LOWER_BYPASS_SET (1<<15)
418 #define RSTPPL_LOWER_PD_SET (1<<14)
419 #define RSTPPL_LOWER_PLL_RESET_SET (1<<13)
420 #define RSTPPL_LOWER_SDRMODE_SET (1<<10)
421 #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
422 #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
423 #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
425 #define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W*/)
426 #define DOTPPL_LOWER_PD_SET (1<<14)
432 #define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
433 #define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
434 #define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
436 #define GLPCI_CTRL (MSR_PCI + 0x2010)
437 #define GLPCI_CTRL_UPPER_FTH_SHIFT 28
438 #define GLPCI_CTRL_UPPER_RTH_SHIFT 24
439 #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
440 #define GLPCI_CTRL_UPPER_DTL_SHIFT 14
441 #define GLPCI_CTRL_UPPER_WTO_SHIFT 11
442 #define GLPCI_CTRL_UPPER_LAT_SHIFT 3
443 #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
444 #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
445 #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
446 #define GLPCI_CTRL_LOWER_ER_SET (1<<11)
447 #define GLPCI_CTRL_LOWER_LDE_SET (1<<9)
448 #define GLPCI_CTRL_LOWER_OWC_SET (1<<4)
449 #define GLPCI_CTRL_LOWER_IWC_SET (1<<3)
450 #define GLPCI_CTRL_LOWER_PCD_SET (1<<2)
451 #define GLPCI_CTRL_LOWER_ME_SET (1<<0)
453 #define GLPCI_ARB (MSR_PCI + 0x2011)
454 #define GLPCI_ARB_UPPER_CR_SHIFT (28)
455 #define GLPCI_ARB_UPPER_R2_SHIFT (24)
456 #define GLPCI_ARB_UPPER_R1_SHIFT (20)
457 #define GLPCI_ARB_UPPER_R0_SHIFT (16)
458 #define GLPCI_ARB_UPPER_CH_SHIFT (12)
459 #define GLPCI_ARB_UPPER_H2_SHIFT (8)
460 #define GLPCI_ARB_UPPER_H1_SHIFT (4)
461 #define GLPCI_ARB_UPPER_H0_SHIFT (0)
462 #define GLPCI_ARB_LOWER_COV_SET (1<<23)
463 #define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
464 #define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
465 #define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
466 #define GLPCI_ARB_LOWER_CPRE_SET (1<<11)
467 #define GLPCI_ARB_LOWER_PRE2_SET (1<<10)
468 #define GLPCI_ARB_LOWER_PRE1_SET (1<<9)
469 #define GLPCI_ARB_LOWER_PRE0_SET (1<<8)
470 #define GLPCI_ARB_LOWER_BM1_SET (1<<7)
471 #define GLPCI_ARB_LOWER_BM0_SET (1<<6)
472 #define GLPCI_ARB_LOWER_PARK_SET (1<<0)
474 #define GLPCI_REN (MSR_PCI + 0x2014)
475 #define GLPCI_A0_BF (MSR_PCI + 0x2015)
476 #define GLPCI_C0_DF (MSR_PCI + 0x2016)
477 #define GLPCI_E0_FF (MSR_PCI + 0x2017)
478 #define GLPCI_RC0 (MSR_PCI + 0x2018)
479 #define GLPCI_RC1 (MSR_PCI + 0x2019)
480 #define GLPCI_RC2 (MSR_PCI + 0x201A)
481 #define GLPCI_RC3 (MSR_PCI + 0x201B)
482 #define GLPCI_RC4 (MSR_PCI + 0x201C)
483 #define GLPCI_RC_UPPER_TOP_SHIFT 12
484 #define GLPCI_RC_LOWER_BASE_SHIFT 12
485 #define GLPCI_RC_LOWER_EN_SET (1<<8)
486 #define GLPCI_RC_LOWER_PF_SET (1<<5)
487 #define GLPCI_RC_LOWER_WC_SET (1<<4)
488 #define GLPCI_RC_LOWER_WP_SET (1<<2)
489 #define GLPCI_RC_LOWER_CD_SET (1<<0)
490 #define GLPCI_EXT_MSR (MSR_PCI + 0x201E)
491 #define GLPCI_SPARE (MSR_PCI + 0x201F)
492 #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
493 #define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
494 #define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
495 #define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
496 #define GLPCI_SPARE_LOWER_MME_SET (1<<2)
497 #define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
498 #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
502 /* FooGlue GLIU1 port 5*/
505 #define FG_GLD_MSR_CAP (MSR_FG + 0x2000)
506 #define FG_GLD_MSR_PM (MSR_FG + 0x2004)
508 /* VIP GLIU1 port 5*/
510 #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
511 #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
512 #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
513 #define VIP_BIST (MSR_VIP + 0x2005)
515 /* AES GLIU1 port 6*/
517 #define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
518 #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
519 #define AES_GLD_MSR_PM (MSR_AES + 0x2004)
520 #define AES_CONTROL (MSR_AES + 0x2006)
522 #define BM 1 /* Base Mask - map power of 2 size aligned region*/
523 #define BMO 2 /* BM with an offset*/
524 #define R 3 /* Range - 4k range minimum*/
525 #define RO 4 /* R with offset*/
526 #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
527 #define BMIO 6 /* Base Mask IO*/
528 #define SCIO 7 /* Swiss 0xCeese IO*/
529 #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/
530 #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/
531 #define BMO_SMM 10 /* Specail marker for SMM*/
532 #define BM_SMM 11 /* Specail marker for SMM*/
533 #define BMO_DMM 12 /* Specail marker for DMM*/
534 #define BM_DMM 13 /* Specail marker for DMM*/
535 #define RO_FB 14 /* special for Frame buffer.*/
536 #define R_FB 15 /* special for FB.*/
537 #define OTHER 0x0FE /* Special marker for other*/
538 #define GL_END 0x0FF /* end*/
540 #define MSR_GL0 (GL1_GLIU0 << 29)
542 /* Set up desc addresses from 20 - 3f*/
543 /* This is chip specific!*/
545 /* ---------- GX3 OK -------------- */
546 #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
547 #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
548 #define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM*/
549 #define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* BM*/
550 #define MSR_GLIU0_BASE5 (MSR_GLIU0 + 0x24) /* BM*/
551 #define MSR_GLIU0_BASE6 (MSR_GLIU0 + 0x25) /* BM*/
553 #define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26)
554 #define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27)
556 #define MSR_GLIU0_SMM (GLIU0_P2D_BMO_0)
557 #define MSR_GLIU0_DMM (GLIU0_P2D_BMO_1)
559 #define GLIU0_P2D_R (MSR_GLIU0 + 0x28)
560 #define MSR_GLIU0_SYSMEM (GLIU0_P2D_R)
562 #define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29)
563 #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A)
564 #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
566 #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
568 #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
569 #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
570 #define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2)
572 #define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3)
573 #define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4)
574 #define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5)
575 #define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6)
576 #define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7)
577 #define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8)
580 #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/
581 #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/
582 #define MSR_GLIU1_BASE3 (MSR_GLIU1 + 0x22) /* BM*/
583 #define MSR_GLIU1_BASE4 (MSR_GLIU1 + 0x23) /* BM*/
584 #define MSR_GLIU1_BASE5 (MSR_GLIU1 + 0x24) /* BM*/
585 #define MSR_GLIU1_BASE6 (MSR_GLIU1 + 0x25) /* BM*/
586 #define MSR_GLIU1_BASE7 (MSR_GLIU1 + 0x26) /* BM*/
587 #define MSR_GLIU1_BASE8 (MSR_GLIU1 + 0x27) /* BM*/
588 #define MSR_GLIU1_BASE9 (MSR_GLIU1 + 0x28) /* BM*/
589 #define MSR_GLIU1_BASE10 (MSR_GLIU1 + 0x29) /* BM*/
591 #define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x2A)
592 #define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2B)
593 #define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2C)
594 #define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2D)
597 #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E)
599 #define MSR_GLIU1_SYSMEM (GLIU1_P2D_R_0)
601 #define MSR_GLIU1_SMM (MSR_GLIU1_BASE4) /* BM*/
602 #define MSR_GLIU1_DMM (MSR_GLIU1_BASE5) /* BM*/
604 #define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0)
605 #define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1)
606 #define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2)
608 #define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3)
609 #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
610 #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
611 #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
613 /* ------------------------ */
615 #define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
618 /* definitions that are "once you are mostly up, start VSA" type things */
619 #define SMM_OFFSET (0x40400000)
620 #define SMM_SIZE (256)
621 #define DMM_OFFSET (0x0C0000000)
622 #define DMM_SIZE (128)
623 #define FB_OFFSET (0x41000000)
624 #define PCI_MEM_TOP (0x0EFFFFFFF) // Top of PCI mem allocation region
625 #define PCI_IO_TOP (0x0EFFF) // Top of PCI I/O allocation region
626 #define END_OPTIONROM_SPACE (0x0DFFF) // E0000 is reserved for SystemROMs.
629 #define CS5535_IDSEL (0x02000000) // IDSEL = AD25, device #15
630 #define CHIPSET_DEV_NUM (15)
631 #define IDSEL_BASE (11) // bit 11 = device 1
634 /* standard AMD post definitions -- might as well use them. */
635 #define POST_Output_Port (0x080) /* port to write post codes to*/
637 #define POST_preSioInit (0x000) /* geode.asm*/
638 #define POST_clockInit (0x001) /* geode.asm*/
639 #define POST_CPURegInit (0x002) /* geode.asm*/
640 #define POST_UNREAL (0x003) /* geode.asm*/
641 #define POST_CPUMemRegInit (0x004) /* geode.asm*/
642 #define POST_CPUTest (0x005) /* geode.asm*/
643 #define POST_memSetup (0x006) /* geode.asm*/
644 #define POST_memSetUpStack (0x007) /* geode.asm*/
645 #define POST_memTest (0x008) /* geode.asm*/
646 #define POST_shadowRom (0x009) /* geode.asm*/
647 #define POST_memRAMoptimize (0x00A) /* geode.asm*/
648 #define POST_cacheInit (0x00B) /* geode.asm*/
649 #define POST_northBridgeInit (0x00C) /* geode.asm*/
650 #define POST_chipsetInit (0x00D) /* geode.asm*/
651 #define POST_sioTest (0x00E) /* geode.asm*/
652 #define POST_pcATjunk (0x00F) /* geode.asm*/
655 #define POST_intTable (0x010) /* geode.asm*/
656 #define POST_memInfo (0x011) /* geode.asm*/
657 #define POST_romCopy (0x012) /* geode.asm*/
658 #define POST_PLLCheck (0x013) /* geode.asm*/
659 #define POST_keyboardInit (0x014) /* geode.asm*/
660 #define POST_cpuCacheOff (0x015) /* geode.asm*/
661 #define POST_BDAInit (0x016) /* geode.asm*/
662 #define POST_pciScan (0x017) /* geode.asm*/
663 #define POST_optionRomInit (0x018) /* geode.asm*/
664 #define POST_ResetLimits (0x019) /* geode.asm*/
665 #define POST_summary_screen (0x01A) /* geode.asm*/
666 #define POST_Boot (0x01B) /* geode.asm*/
667 #define POST_SystemPreInit (0x01C) /* geode.asm*/
668 #define POST_ClearRebootFlag (0x01D) /* geode.asm*/
669 #define POST_GLIUInit (0x01E) /* geode.asm*/
670 #define POST_BootFailed (0x01F) /* geode.asm*/
673 #define POST_CPU_ID (0x020) /* cpucpuid.asm*/
674 #define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/
675 #define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/
676 #define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/
677 #define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/
678 #define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/
679 #define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/
680 #define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/
681 #define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/
682 #define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/
683 #define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/
684 #define POST_CHIPSET_ID (0x02b) /* chipset.asm*/
685 #define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/
686 #define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/
687 #define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/
688 #define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/
693 #define P80_PCICFG (0x030) /* pcispace.asm*/
697 #define P80_PCIIO (0x040) /* pcispace.asm*/
701 #define P80_PCIMEM (0x050) /* pcispace.asm*/
705 #define P80_SIO (0x060) /* *sio.asm*/
708 #define P80_MEM_SETUP (0x070) /* docboot meminit*/
709 #define POST_MEM_SETUP (0x070) /* memsize.asm*/
710 #define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/
711 #define POST_MEM_SETUP2 (0x072) /* memsize.asm*/
712 #define POST_MEM_SETUP3 (0x073) /* memsize.asm*/
713 #define POST_MEM_SETUP4 (0x074) /* memsize.asm*/
714 #define POST_MEM_SETUP5 (0x075) /* memsize.asm*/
715 #define POST_MEM_ENABLE (0x076) /* memsize.asm*/
716 #define ERROR_NO_DIMMS (0x077) /* memsize.asm*/
717 #define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/
718 #define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/
719 #define ERROR_SET_PAGE (0x07a) /* memsize.asm*/
720 #define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/
721 #define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/
722 #define ERROR_BANK_SET (0x07d) /* memsize.asm*/
723 #define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/
724 #define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/
727 #define POST_UserPreInit (0x080) /* geode.asm*/
728 #define POST_UserPostInit (0x081) /* geode.asm*/
729 #define POST_Equipment_check (0x082) /* geode.asm*/
730 #define POST_InitNVRAMBX (0x083) /* geode.asm*/
731 #define POST_NoPIRTable (0x084) /* pci.asm*/
732 #define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/
733 #define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/
734 #define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/
735 #define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/
736 #define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/
737 #define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/
738 #define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/
739 #define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/
740 #define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/
741 #define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/
744 #define POST_STACK_SETUP (0x090) /* memstack.asm*/
745 #define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/
746 #define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/
747 #define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/
748 #define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/
749 #define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/
750 #define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/
751 #define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/
752 #define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/
755 #define POST_PLL_INIT (0x0A0) /* pllinit.asm*/
756 #define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/
757 #define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/
758 #define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/
759 #define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/
760 #define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/
761 #define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/
764 #define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/
765 #define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/
766 #define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/
767 #define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/
768 #define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/
769 #define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/
770 #define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/
773 #define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/
774 #define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/
775 #define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/
776 #define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/
777 #define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/
778 #define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/
779 #define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/
780 #define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/
781 #define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/
782 #define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/
783 #define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/
784 #define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/
785 #define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/
786 #define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/
788 #define POST_RCONFInitError (0x0CE) /* cache.asm*/
789 #define POST_CacheInitError (0x0CF) /* cache.asm*/
792 #define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/
793 #define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/
794 #define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/
795 #define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/
796 #define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/
797 #define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/
798 #define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/
799 #define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/
800 #define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/
801 #define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/
802 #define POST_ROM_POSTUNCOMPRESS (0x0DE)
805 #define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/
806 #define POST_PreChipsetInit (0x0E1) /* geode.asm*/
807 #define POST_LateChipsetInit (0x0E2) /* geode.asm*/
808 #define POST_NORTHB_INIT (0x0E8) /* northb.asm*/
811 #define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/
814 /* I don't mind if somebody decides this needs to be in a seperate file. I don't see much point
818 #define Cx5535_ID ( 0x002A100B)
819 #define Cx5536_ID ( 0x208F1022)
821 /* Cs5535 as follows. */
825 /* port2 - USB Controller #2*/
826 /* port3 - ATA-5 Controller*/
829 /* port6 - USB Controller #1*/
833 /* SouthBridge Equates*/
834 /* MSR_SB and SB_SHIFT are located in CPU.inc*/
835 #define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
836 #define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
837 #define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
838 #define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
839 #define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
840 #define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
841 #define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
842 #define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
847 #define GLIU_SB_GLD_MSR_CAP ( MSR_SB_GLIU + 0x00)
848 #define GLIU_SB_GLD_MSR_CONF ( MSR_SB_GLIU + 0x01)
849 #define GLIU_SB_GLD_MSR_PM ( MSR_SB_GLIU + 0x04)
854 #define USB1_SB_GLD_MSR_CAP ( MSR_SB_USB1 + 0x00)
855 #define USB1_SB_GLD_MSR_CONF ( MSR_SB_USB1 + 0x01)
856 #define USB1_SB_GLD_MSR_PM ( MSR_SB_USB1 + 0x04)
860 #define USB2_SB_GLD_MSR_CAP ( MSR_SB_USB2 + 0x00)
861 #define USB2_SB_GLD_MSR_CONF ( MSR_SB_USB2 + 0x01)
862 #define USB2_SB_GLD_MSR_PM ( MSR_SB_USB2 + 0x04)
868 #define ATA_SB_GLD_MSR_CAP ( MSR_SB_ATA + 0x00)
869 #define ATA_SB_GLD_MSR_CONF ( MSR_SB_ATA + 0x01)
870 #define ATA_SB_GLD_MSR_ERR ( MSR_SB_ATA + 0x03)
871 #define ATA_SB_GLD_MSR_PM ( MSR_SB_ATA + 0x04)
876 #define AC97_SB_GLD_MSR_CAP ( MSR_SB_AC97 + 0x00)
877 #define AC97_SB_GLD_MSR_CONF ( MSR_SB_AC97 + 0x01)
878 #define AC97_SB_GLD_MSR_PM ( MSR_SB_AC97 + 0x04)
883 #define GLPCI_SB_GLD_MSR_CAP ( MSR_SB_GLPCI + 0x00)
884 #define GLPCI_SB_GLD_MSR_CONF ( MSR_SB_GLPCI + 0x01)
885 #define GLPCI_SB_GLD_MSR_PM ( MSR_SB_GLPCI + 0x04)
886 #define GLPCI_SB_CTRL ( MSR_SB_GLPCI + 0x10)
887 #define GLPCI_CRTL_PPIDE_SET ( 1 << 17)
891 #define GLCP_SB_GLD_MSR_CAP ( MSR_SB_GLCP + 0x00)
892 #define GLCP_SB_GLD_MSR_CONF ( MSR_SB_GLCP + 0x01)
893 #define GLCP_SB_GLD_MSR_PM ( MSR_SB_GLCP + 0x04)
899 #define MDD_SMBUS (0x6000)
900 #define MDD_GPIO (0x6100)
901 #define MDD_MFGPT (0x6200)
902 #define MDD_FLASH_BAR_0 (0x6400)
903 #define MDD_FLASH_BAR_1 (0x6500)
904 #define MDD_FLASH_BAR_2 (0x6600)
905 #define MDD_FLASH_BAR_3 (0x6700)
907 #define MDD_ACPI_BASE (0x9C00)
908 #define MDD_PM (0x9D00)
912 #define GPIO_BASE MDD_GPIO
913 #define ACPI_BASE MDD_ACPI_BASE
914 #define PMLogic_BASE MDD_PM
917 #define MDD_SB_GLD_MSR_CAP ( MSR_SB_MDD + 0x00)
918 #define MDD_SB_GLD_MSR_CONF ( MSR_SB_MDD + 0x01)
919 #define MDD_SB_GLD_MSR_PM ( MSR_SB_MDD + 0x04)
920 #define LBAR_EN ( 0x01)
921 #define IO_MASK ( 0x1f)
922 #define MEM_MASK ( 0x0FFFFF)
923 #define MDD_LBAR_IRQ ( MSR_SB_MDD + 0x08)
924 #define MDD_LBAR_KEL1 ( MSR_SB_MDD + 0x09)
925 #define MDD_LBAR_KEL2 ( MSR_SB_MDD + 0x0A)
926 #define MDD_LBAR_SMB ( MSR_SB_MDD + 0x0B)
927 #define MDD_LBAR_GPIO ( MSR_SB_MDD + 0x0C)
928 #define MDD_LBAR_MFGPT ( MSR_SB_MDD + 0x0D)
929 #define MDD_LBAR_ACPI ( MSR_SB_MDD + 0x0E)
930 #define MDD_LBAR_PMS ( MSR_SB_MDD + 0x0F)
932 #define MDD_LBAR_FLSH0 ( MSR_SB_MDD + 0x010)
933 #define MDD_LBAR_FLSH1 ( MSR_SB_MDD + 0x011)
934 #define MDD_LBAR_FLSH2 ( MSR_SB_MDD + 0x012)
935 #define MDD_LBAR_FLSH3 ( MSR_SB_MDD + 0x013)
936 #define MDD_LEG_IO ( MSR_SB_MDD + 0x014)
937 #define MDD_PIN_OPT ( MSR_SB_MDD + 0x015)
938 #define MDD_SOFT_IRQ ( MSR_SB_MDD + 0x016)
939 #define MDD_SOFT_RESET ( MSR_SB_MDD + 0x017)
940 #define MDD_NORF_CNTRL ( MSR_SB_MDD + 0x018)
941 #define MDD_NORF_T01 ( MSR_SB_MDD + 0x019)
942 #define MDD_NORF_T23 ( MSR_SB_MDD + 0x01A)
943 #define MDD_NANDF_DATA ( MSR_SB_MDD + 0x01B)
944 #define MDD_NADF_CNTL ( MSR_SB_MDD + 0x01C)
945 #define MDD_AC_DMA ( MSR_SB_MDD + 0x01E)
946 #define MDD_KEL_CNTRL ( MSR_SB_MDD + 0x01F)
948 #define MDD_IRQM_YLOW ( MSR_SB_MDD + 0x020)
949 #define MDD_IRQM_YHIGH ( MSR_SB_MDD + 0x021)
950 #define MDD_IRQM_ZLOW ( MSR_SB_MDD + 0x022)
951 #define MDD_IRQM_ZHIGH ( MSR_SB_MDD + 0x023)
952 #define MDD_IRQM_PRIM ( MSR_SB_MDD + 0x024)
953 #define MDD_IRQM_LPC ( MSR_SB_MDD + 0x025)
954 #define MDD_IRQM_LXIRR ( MSR_SB_MDD + 0x026)
955 #define MDD_IRQM_HXIRR ( MSR_SB_MDD + 0x027)
957 #define MDD_MFGPT_IRQ ( MSR_SB_MDD + 0x028)
958 #define MDD_MFGPT_NR ( MSR_SB_MDD + 0x029)
959 #define MDD_MFGPT_RES0 ( MSR_SB_MDD + 0x02A)
960 #define MDD_MFGPT_RES1 ( MSR_SB_MDD + 0x02B)
962 #define MDD_FLOP_S3F2 ( MSR_SB_MDD + 0x030)
963 #define MDD_FLOP_S3F7 ( MSR_SB_MDD + 0x031)
964 #define MDD_FLOP_S372 ( MSR_SB_MDD + 0x032)
965 #define MDD_FLOP_S377 ( MSR_SB_MDD + 0x033)
967 #define MDD_PIC_S ( MSR_SB_MDD + 0x034)
968 #define MDD_PIT_S ( MSR_SB_MDD + 0x036)
969 #define MDD_PIT_CNTRL ( MSR_SB_MDD + 0x037)
971 #define MDD_UART1_MOD ( MSR_SB_MDD + 0x038)
972 #define MDD_UART1_DON ( MSR_SB_MDD + 0x039)
973 #define MDD_UART1_CONF ( MSR_SB_MDD + 0x03A)
974 #define MDD_UART2_MOD ( MSR_SB_MDD + 0x03C)
975 #define MDD_UART2_DON ( MSR_SB_MDD + 0x03D)
976 #define MDD_UART2_CONF ( MSR_SB_MDD + 0x03E)
978 #define MDD_DMA_MAP ( MSR_SB_MDD + 0x040)
979 #define MDD_DMA_SHAD1 ( MSR_SB_MDD + 0x041)
980 #define MDD_DMA_SHAD2 ( MSR_SB_MDD + 0x042)
981 #define MDD_DMA_SHAD3 ( MSR_SB_MDD + 0x043)
982 #define MDD_DMA_SHAD4 ( MSR_SB_MDD + 0x044)
983 #define MDD_DMA_SHAD5 ( MSR_SB_MDD + 0x045)
984 #define MDD_DMA_SHAD6 ( MSR_SB_MDD + 0x046)
985 #define MDD_DMA_SHAD7 ( MSR_SB_MDD + 0x047)
986 #define MDD_DMA_SHAD8 ( MSR_SB_MDD + 0x048)
987 #define MDD_DMA_SHAD9 ( MSR_SB_MDD + 0x049)
989 #define MDD_LPC_EADDR ( MSR_SB_MDD + 0x04C)
990 #define MDD_LPC_ESTAT ( MSR_SB_MDD + 0x04D)
991 #define MDD_LPC_SIRQ ( MSR_SB_MDD + 0x04E)
992 #define MDD_LPC_RES ( MSR_SB_MDD + 0x04F)
994 #define MDD_PML_TMR ( MSR_SB_MDD + 0x050)
995 #define MDD_RTC_RAM_LO_CK ( MSR_SB_MDD + 0x054)
996 #define MDD_RTC_DOMA_IND ( MSR_SB_MDD + 0x055)
997 #define MDD_RTC_MONA_IND ( MSR_SB_MDD + 0x056)
998 #define MDD_RTC_CENTURY_OFFSET ( MSR_SB_MDD + 0x057)
1000 /* ***********************************************************/
1001 /* LBUS Device Equates - */
1002 /* ***********************************************************/
1008 #define SMBUS_SMBSDA ( SMBUS_BASE + 0x00)
1009 #define SMBUS_SMBST ( SMBUS_BASE + 0x01)
1010 #define SMBST_SLVSTP_SET ( 1 << 7)
1011 #define SMBST_SDAST_SET ( 1 << 6)
1012 #define SMBST_BER_SET ( 1 << 5)
1013 #define SMBST_NEGACK_SET ( 1 << 4)
1014 #define SMBST_STASTR_SET ( 1 << 3)
1015 #define SMBST_NMATCH_SET ( 1 << 2)
1016 #define SMBST_MASTER_SET ( 1 << 1)
1017 #define SMBST_XMIT_SET ( 1 << 0)
1018 #define SMBUS_SMBCST ( SMBUS_BASE + 0x02)
1019 #define SMBCST_TGSCL_SET ( 1 << 5)
1020 #define SMBCST_TSDA_SET ( 1 << 4)
1021 #define SMBCST_GCMTCH_SET ( 1 << 3)
1022 #define SMBCST_MATCH_SET ( 1 << 2)
1023 #define SMBCST_BB_SET ( 1 << 1)
1024 #define SMBCST_BUSY_SET ( 1 << 0)
1025 #define SMBUS_SMBCTL1 ( SMBUS_BASE + 0x03)
1026 #define SMBCTL1_STASTRE_SET ( 1 << 7)
1027 #define SMBCTL1_NMINTE_SET ( 1 << 6)
1028 #define SMBCTL1_GCMEN_SET ( 1 << 5)
1029 #define SMBCTL1_RECACK_SET ( 1 << 4)
1030 #define SMBCTL1_DMAEN_SET ( 1 << 3)
1031 #define SMBCTL1_INTEN_SET ( 1 << 2)
1032 #define SMBCTL1_STOP_SET ( 1 << 1)
1033 #define SMBCTL1_START_SET ( 1 << 0)
1034 #define SMBUS_SMBADDR ( SMBUS_BASE + 0x04)
1035 #define SMBADDR_SAEN_SET ( 1 << 7)
1036 #define SMBUS_SMBCTL2 ( SMBUS_BASE + 0x05)
1037 #define SMBCTL2_SCLFRQ_SHIFT ( 1 << 1)
1038 #define SMBCTL2_ENABLE_SET ( 1 << 0)
1044 #define GPIOL_0_SET ( 1 << 0)
1045 #define GPIOL_1_SET ( 1 << 1)
1046 #define GPIOL_2_SET ( 1 << 2)
1047 #define GPIOL_3_SET ( 1 << 3)
1048 #define GPIOL_4_SET ( 1 << 4)
1049 #define GPIOL_5_SET ( 1 << 5)
1050 #define GPIOL_6_SET ( 1 << 6)
1051 #define GPIOL_7_SET ( 1 << 7)
1052 #define GPIOL_8_SET ( 1 << 8)
1053 #define GPIOL_9_SET ( 1 << 9)
1054 #define GPIOL_10_SET ( 1 << 10)
1055 #define GPIOL_11_SET ( 1 << 11)
1056 #define GPIOL_12_SET ( 1 << 12)
1057 #define GPIOL_13_SET ( 1 << 13)
1058 #define GPIOL_14_SET ( 1 << 14)
1059 #define GPIOL_15_SET ( 1 << 15)
1061 #define GPIOL_0_CLEAR ( 1 << 16)
1062 #define GPIOL_1_CLEAR ( 1 << 17)
1063 #define GPIOL_2_CLEAR ( 1 << 18)
1064 #define GPIOL_3_CLEAR ( 1 << 19)
1065 #define GPIOL_4_CLEAR ( 1 << 20)
1066 #define GPIOL_5_CLEAR ( 1 << 21)
1067 #define GPIOL_6_CLEAR ( 1 << 22)
1068 #define GPIOL_7_CLEAR ( 1 << 23)
1069 #define GPIOL_8_CLEAR ( 1 << 24)
1070 #define GPIOL_9_CLEAR ( 1 << 25)
1071 #define GPIOL_10_CLEAR ( 1 << 26)
1072 #define GPIOL_11_CLEAR ( 1 << 27)
1073 #define GPIOL_12_CLEAR ( 1 << 28)
1074 #define GPIOL_13_CLEAR ( 1 << 29)
1075 #define GPIOL_14_CLEAR ( 1 << 30)
1076 #define GPIOL_15_CLEAR ( 1 << 31)
1078 #define GPIOH_16_SET ( 1 << 0)
1079 #define GPIOH_17_SET ( 1 << 1)
1080 #define GPIOH_18_SET ( 1 << 2)
1081 #define GPIOH_19_SET ( 1 << 3)
1082 #define GPIOH_20_SET ( 1 << 4)
1083 #define GPIOH_21_SET ( 1 << 5)
1084 #define GPIOH_22_SET ( 1 << 6)
1085 #define GPIOH_23_SET ( 1 << 7)
1086 #define GPIOH_24_SET ( 1 << 8)
1087 #define GPIOH_25_SET ( 1 << 9)
1088 #define GPIOH_26_SET ( 1 << 10)
1089 #define GPIOH_27_SET ( 1 << 11)
1090 #define GPIOH_28_SET ( 1 << 12)
1091 #define GPIOH_29_SET ( 1 << 13)
1092 #define GPIOH_30_SET ( 1 << 14)
1093 #define GPIOH_31_SET ( 1 << 15)
1095 #define GPIOH_16_CLEAR ( 1 << 16)
1096 #define GPIOH_17_CLEAR ( 1 << 17)
1097 #define GPIOH_18_CLEAR ( 1 << 18)
1098 #define GPIOH_19_CLEAR ( 1 << 19)
1099 #define GPIOH_20_CLEAR ( 1 << 20)
1100 #define GPIOH_21_CLEAR ( 1 << 21)
1101 #define GPIOH_22_CLEAR ( 1 << 22)
1102 #define GPIOH_23_CLEAR ( 1 << 23)
1103 #define GPIOH_24_CLEAR ( 1 << 24)
1104 #define GPIOH_25_CLEAR ( 1 << 25)
1105 #define GPIOH_26_CLEAR ( 1 << 26)
1106 #define GPIOH_27_CLEAR ( 1 << 27)
1107 #define GPIOH_28_CLEAR ( 1 << 28)
1108 #define GPIOH_29_CLEAR ( 1 << 29)
1109 #define GPIOH_30_CLEAR ( 1 << 30)
1110 #define GPIOH_31_CLEAR ( 1 << 31)
1113 /* GPIO LOW Bank Bit Registers*/
1114 #define GPIOL_OUTPUT_VALUE ( GPIO_BASE + 0x00)
1115 #define GPIOL_OUTPUT_ENABLE ( GPIO_BASE + 0x04)
1116 #define GPIOL_OUT_OPENDRAIN ( GPIO_BASE + 0x08)
1117 #define GPIOL_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x0C)
1118 #define GPIOL_OUT_AUX1_SELECT ( GPIO_BASE + 0x10)
1119 #define GPIOL_OUT_AUX2_SELECT ( GPIO_BASE + 0x14)
1120 #define GPIOL_PULLUP_ENABLE ( GPIO_BASE + 0x18)
1121 #define GPIOL_PULLDOWN_ENABLE ( GPIO_BASE + 0x1C)
1122 #define GPIOL_INPUT_ENABLE ( GPIO_BASE + 0x20)
1123 #define GPIOL_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x24)
1124 #define GPIOL_IN_FILTER_ENABLE ( GPIO_BASE + 0x28)
1125 #define GPIOL_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x2C)
1126 #define GPIOL_READ_BACK ( GPIO_BASE + 0x30)
1127 #define GPIOL_IN_AUX1_SELECT ( GPIO_BASE + 0x34)
1128 #define GPIOL_EVENTS_ENABLE ( GPIO_BASE + 0x38)
1129 #define GPIOL_LOCK_ENABLE ( GPIO_BASE + 0x3C)
1130 #define GPIOL_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x40)
1131 #define GPIOL_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x44)
1132 #define GPIOL_IN_POSEDGE_STATUS ( GPIO_BASE + 0x48)
1133 #define GPIOL_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x4C)
1135 /* GPIO High Bank Bit Registers*/
1136 #define GPIOH_OUTPUT_VALUE ( GPIO_BASE + 0x80)
1137 #define GPIOH_OUTPUT_ENABLE ( GPIO_BASE + 0x84)
1138 #define GPIOH_OUT_OPENDRAIN ( GPIO_BASE + 0x88)
1139 #define GPIOH_OUTPUT_INVERT_ENABLE ( GPIO_BASE + 0x8C)
1140 #define GPIOH_OUT_AUX1_SELECT ( GPIO_BASE + 0x90)
1141 #define GPIOH_OUT_AUX2_SELECT ( GPIO_BASE + 0x94)
1142 #define GPIOH_PULLUP_ENABLE ( GPIO_BASE + 0x98)
1143 #define GPIOH_PULLDOWN_ENABLE ( GPIO_BASE + 0x9C)
1144 #define GPIOH_INPUT_ENABLE ( GPIO_BASE + 0x0A0)
1145 #define GPIOH_INPUT_INVERT_ENABLE ( GPIO_BASE + 0x0A4)
1146 #define GPIOH_IN_FILTER_ENABLE ( GPIO_BASE + 0x0A8)
1147 #define GPIOH_IN_EVENTCOUNT_ENABLE ( GPIO_BASE + 0x0AC)
1148 #define GPIOH_READ_BACK ( GPIO_BASE + 0x0B0)
1149 #define GPIOH_IN_AUX1_SELECT ( GPIO_BASE + 0x0B4)
1150 #define GPIOH_EVENTS_ENABLE ( GPIO_BASE + 0x0B8)
1151 #define GPIOH_LOCK_ENABLE ( GPIO_BASE + 0x0BC)
1152 #define GPIOH_IN_POSEDGE_ENABLE ( GPIO_BASE + 0x0C0)
1153 #define GPIOH_IN_NEGEDGE_ENABLE ( GPIO_BASE + 0x0C4)
1154 #define GPIOH_IN_POSEDGE_STATUS ( GPIO_BASE + 0x0C8)
1155 #define GPIOH_IN_NEGEDGE_STATUS ( GPIO_BASE + 0x0CC)
1157 /* Input Conditioning Function Registers*/
1158 #define GPIO_00_FILTER_AMOUNT ( GPIO_BASE + 0x50)
1159 #define GPIO_00_FILTER_COUNT ( GPIO_BASE + 0x52)
1160 #define GPIO_00_EVENT_COUNT ( GPIO_BASE + 0x54)
1161 #define GPIO_00_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x56)
1162 #define GPIO_01_FILTER_AMOUNT ( GPIO_BASE + 0x58)
1163 #define GPIO_01_FILTER_COUNT ( GPIO_BASE + 0x5A)
1164 #define GPIO_01_EVENT_COUNT ( GPIO_BASE + 0x5C)
1165 #define GPIO_01_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x5E)
1166 #define GPIO_02_FILTER_AMOUNT ( GPIO_BASE + 0x60)
1167 #define GPIO_02_FILTER_COUNT ( GPIO_BASE + 0x62)
1168 #define GPIO_02_EVENT_COUNT ( GPIO_BASE + 0x64)
1169 #define GPIO_02_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x66)
1170 #define GPIO_03_FILTER_AMOUNT ( GPIO_BASE + 0x68)
1171 #define GPIO_03_FILTER_COUNT ( GPIO_BASE + 0x6A)
1172 #define GPIO_03_EVENT_COUNT ( GPIO_BASE + 0x6C)
1173 #define GPIO_03_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x6E)
1174 #define GPIO_04_FILTER_AMOUNT ( GPIO_BASE + 0x70)
1175 #define GPIO_04_FILTER_COUNT ( GPIO_BASE + 0x72)
1176 #define GPIO_04_EVENT_COUNT ( GPIO_BASE + 0x74)
1177 #define GPIO_04_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x76)
1178 #define GPIO_05_FILTER_AMOUNT ( GPIO_BASE + 0x78)
1179 #define GPIO_05_FILTER_COUNT ( GPIO_BASE + 0x7A)
1180 #define GPIO_05_EVENT_COUNT ( GPIO_BASE + 0x7C)
1181 #define GPIO_05_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x7E)
1182 #define GPIO_06_FILTER_AMOUNT ( GPIO_BASE + 0x0D0)
1183 #define GPIO_06_FILTER_COUNT ( GPIO_BASE + 0x0D2)
1184 #define GPIO_06_EVENT_COUNT ( GPIO_BASE + 0x0D4)
1185 #define GPIO_06_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0D6)
1186 #define GPIO_07_FILTER_AMOUNT ( GPIO_BASE + 0x0D8)
1187 #define GPIO_07_FILTER_COUNT ( GPIO_BASE + 0x0DA)
1188 #define GPIO_07_EVENT_COUNT ( GPIO_BASE + 0x0DC)
1189 #define GPIO_07_EVENTCOMPARE_VALUE ( GPIO_BASE + 0x0DE)
1191 /* R/W GPIO Interrupt &PME Mapper Registers*/
1192 #define GPIO_MAPPER_X ( GPIO_BASE + 0x0E0)
1193 #define GPIO_MAPPER_Y ( GPIO_BASE + 0x0E4)
1194 #define GPIO_MAPPER_Z ( GPIO_BASE + 0x0E8)
1195 #define GPIO_MAPPER_W ( GPIO_BASE + 0x0EC)
1196 #define GPIO_FE_SELECT_0 ( GPIO_BASE + 0x0F0)
1197 #define GPIO_FE_SELECT_1 ( GPIO_BASE + 0x0F1)
1198 #define GPIO_FE_SELECT_2 ( GPIO_BASE + 0x0F2)
1199 #define GPIO_FE_SELECT_3 ( GPIO_BASE + 0x0F3)
1200 #define GPIO_FE_SELECT_4 ( GPIO_BASE + 0x0F4)
1201 #define GPIO_FE_SELECT_5 ( GPIO_BASE + 0x0F5)
1202 #define GPIO_FE_SELECT_6 ( GPIO_BASE + 0x0F6)
1203 #define GPIO_FE_SELECT_7 ( GPIO_BASE + 0x0F7)
1205 /* Event Counter Decrement Registers*/
1206 #define GPIOL_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0F8)
1207 #define GPIOH_IN_EVENT_DECREMENT ( GPIO_BASE + 0x0FC)
1209 /* This is for 286reset compatibility. 0xCange to mat0xc 5535 virtualized stuff.*/
1210 #define FUNC0 ( 0x90)
1213 /* sworley, PMC register*/
1214 #define PM_SSD ( PMLogic_BASE + 0x00)
1215 #define PM_SCXA ( PMLogic_BASE + 0x04)
1216 #define PM_SCYA ( PMLogic_BASE + 0x08)
1217 #define PM_SODA ( PMLogic_BASE + 0x0C)
1218 #define PM_SCLK ( PMLogic_BASE + 0x10)
1219 #define PM_SED ( PMLogic_BASE + 0x14)
1220 #define PM_SCXD ( PMLogic_BASE + 0x18)
1221 #define PM_SCYD ( PMLogic_BASE + 0x1C)
1222 #define PM_SIDD ( PMLogic_BASE + 0x20)
1223 #define PM_WKD ( PMLogic_BASE + 0x30)
1224 #define PM_WKXD ( PMLogic_BASE + 0x34)
1225 #define PM_RD ( PMLogic_BASE + 0x38)
1226 #define PM_WKXA ( PMLogic_BASE + 0x3C)
1227 #define PM_FSD ( PMLogic_BASE + 0x40)
1228 #define PM_TSD ( PMLogic_BASE + 0x44)
1229 #define PM_PSD ( PMLogic_BASE + 0x48)
1230 #define PM_NWKD ( PMLogic_BASE + 0x4C)
1231 #define PM_AWKD ( PMLogic_BASE + 0x50)
1232 #define PM_SSC ( PMLogic_BASE + 0x54)
1235 /* FLASH device macros */
1236 #define FLASH_TYPE_NONE 0 /* No flash device installed */
1237 #define FLASH_TYPE_NAND 1 /* NAND device */
1238 #define FLASH_TYPE_NOR 2 /* NOR device */
1240 #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
1241 #define FLASH_IF_IO 2 /* I/O interface for Flash device */
1243 /* Flash Memory Mask values */
1244 #define FLASH_MEM_DEFAULT 0x00000000
1245 #define FLASH_MEM_4K 0xFFFFF000
1246 #define FLASH_MEM_8K 0xFFFFE000
1247 #define FLASH_MEM_16K 0xFFFFC000
1248 #define FLASH_MEM_128K 0xFFFE0000
1249 #define FLASH_MEM_512K 0xFFFC0000
1250 #define FLASH_MEM_4M 0xFFC00000
1251 #define FLASH_MEM_8M 0xFF800000
1252 #define FLASH_MEM_16M 0xFF000000
1254 /* Flash IO Mask values */
1255 #define FLASH_IO_DEFAULT 0x00000000
1256 #define FLASH_IO_16B 0x0000FFF0
1257 #define FLASH_IO_32B 0x0000FFE0
1258 #define FLASH_IO_64B 0x0000FFC0
1259 #define FLASH_IO_128B 0x0000FF80
1260 #define FLASH_IO_256B 0x0000FF00
1264 #endif /* CPU_AMD_LXDEF_H */