2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
5 * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2006 Stefan Reinauer <stepan@coresystems.de>
7 * Copyright (C) 2006 Andrei Birjukov <andrei.birjukov@artecdesign.ee>
8 * Copyright (C) 2007 Advanced Micro Devices, Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #ifndef CPU_AMD_LXDEF_H
26 #define CPU_AMD_LXDEF_H
28 #define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/
29 #define CPU_ID_2_0 0x000005A1
30 #define CPU_ID_3_0 0x000005A2
32 #define CPU_REV_1_0 0x010
33 #define CPU_REV_1_1 0x011
34 #define CPU_REV_2_0 0x020
35 #define CPU_REV_2_1 0x021
36 #define CPU_REV_2_2 0x022
37 #define CPU_REV_C_0 0x030
38 #define CPU_REV_C_1 0x031
39 #define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/
40 #define CPU_REV_C_3 0x033
43 /* MSR routing as follows*/
44 /* MSB = 1 means not for CPU*/
45 /* next 3 bits 1st port*/
46 /* next3 bits next port if through an GLIU*/
66 #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */
67 #define MSR_MC (GL0_MC << 29) /* 2000xxxx */
68 #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
69 #define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/
70 #define MSR_VG (GL0_VG << 29) /* 8000xxxx */
71 #define MSR_GP (GL0_GP << 29) /* A000xxxx */
73 #define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */
74 #define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
75 #define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
76 #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
77 #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
78 #define MSR_FG MSR_GLCP
80 /*GeodeLink Interface Unit 0 (GLIU0) port0*/
82 #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
83 #define GLIU0_GLD_MSR_ERROR (MSR_GLIU0 + 0x2003)
84 #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
86 #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20)
87 #define GLIU0_CAP (MSR_GLIU0 + 0x86)
88 #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
89 #define GLIU0_ARB (MSR_GLIU0 + 0x82)
90 #define ARB_UPPER_QUACK_EN_SET (1 << 31)
91 #define ARB_UPPER_DACK_EN_SET (1 << 28)
94 /* Memory Controller GLIU0 port 1*/
96 #define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
97 #define MC_GLD_MSR_PM (MSR_MC + 0x2004)
99 #define MC_CF07_DATA (MSR_MC + 0x18)
100 #define CF07_UPPER_D1_SZ_SHIFT 28
101 #define CF07_UPPER_D1_MB_SHIFT 24
102 #define CF07_UPPER_D1_CB_SHIFT 20
103 #define CF07_UPPER_D1_PSZ_SHIFT 16
104 #define CF07_UPPER_D0_SZ_SHIFT 12
105 #define CF07_UPPER_D0_MB_SHIFT 8
106 #define CF07_UPPER_D0_CB_SHIFT 4
107 #define CF07_UPPER_D0_PSZ_SHIFT 0
109 #define CF07_LOWER_REF_INT_SHIFT 8
110 #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
111 #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
112 #define CF07_LOWER_EMR_QFC_SET (1 << 26)
113 #define CF07_LOWER_EMR_DRV_SET (1 << 25)
114 #define CF07_LOWER_REF_TEST_SET (1 << 3)
115 #define CF07_LOWER_PROG_DRAM_SET (1 << 0)
118 #define MC_CF8F_DATA (MSR_MC + 0x19)
119 #define CF8F_UPPER_XOR_BS_SHIFT 19
120 #define CF8F_UPPER_XOR_MB0_SHIFT 18
121 #define CF8F_UPPER_XOR_BA1_SHIFT 17
122 #define CF8F_UPPER_XOR_BA0_SHIFT 16
123 #define CF8F_UPPER_REORDER_DIS_SET (1 << 8)
124 #define CF8F_LOWER_CAS_LAT_SHIFT 28
125 #define CF8F_LOWER_ACT2ACTREF_SHIFT 24
126 #define CF8F_LOWER_ACT2PRE_SHIFT 20
127 #define CF8F_LOWER_PRE2ACT_SHIFT 16
128 #define CF8F_LOWER_ACT2CMD_SHIFT 12
129 #define CF8F_LOWER_ACT2ACT_SHIFT 8
130 #define CF8F_UPPER_HOI_LOI_SET (1 << 1)
132 #define MC_CF1017_DATA (MSR_MC + 0x1A)
133 #define CF1017_LOWER_WR_TO_RD_SHIFT 28
134 #define CF1017_LOWER_RD_TMG_CTL_SHIFT 24
135 #define CF1017_LOWER_REF2ACT_SHIFT 16
136 #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
137 #define CF1017_LOWER_WR2DAT_SHIFT 0
139 #define MC_CFCLK_DBUG (MSR_MC + 0x1D)
141 #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
142 #define CFCLK_UPPER_MTST_RBEX_EN_SET (1 << 1)
143 #define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
145 #define CFCLK_LOWER_FORCE_PRE_SET (1 << 16)
146 #define CFCLK_LOWER_TRISTATE_DIS_SET (1 << 12)
147 #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
148 #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
149 #define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
151 #define MC_CF_RDSYNC (MSR_MC + 0x1F)
152 #define MC_CF_PMCTR (MSR_MC + 0x20)
155 /* GLIU1 GLIU0 port2*/
157 #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
158 #define GLIU1_GLD_MSR_ERROR (MSR_GLIU1 + 0x2003)
159 #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
161 #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
162 #define GLIU1_PORT_ACTIVE (MSR_GLIU1 + 0x81)
163 #define GLIU1_ARB (MSR_GLIU1 + 0x82)
167 /* CPU ; does not need routing instructions since we are executing there.*/
169 #define CPU_GLD_MSR_CAP 0x2000
170 #define CPU_GLD_MSR_CONFIG 0x2001
171 #define CPU_GLD_MSR_PM 0x2004
173 #define CPU_GLD_MSR_DIAG 0x2005
174 #define DIAG_SEL1_MODE_SHIFT 16
175 #define DIAG_SEL1_SET (1 << 31)
176 #define DIAG_SEL0__MODE_SHIFT 0
177 #define DIAG_SET0_SET (1 << 15)
179 #define CPU_PF_CONF 0x1100
180 #define RETURN_STACK_ENABLE_SET (1 << 4)
181 #define PF_CONF_CC_L1 (1 << 0)
182 #define CPU_PF_INVD 0x1102
183 #define PF_RS_INVD_SET (1 << 1)
184 #define PF_CC_INVD_SET (1 << 0)
185 #define CPU_PF_BIST 0x1140
187 #define CPU_XC_CONFIG 0x1210
188 #define XC_CONFIG_SUSP_ON_HLT (1 << 0)
189 #define XC_CONFIG_SUSP_ON_PAUSE (1 << 1)
191 #define CPU_ID_CONFIG 0x1250
192 #define ID_CONFIG_SERIAL_SET (1 << 0)
194 #define CPU_AC_MSR 0x1301
197 #define CPU_AC_SMM_CTL 0x1301
198 #define SMM_NMI_EN_SET (1 << 0)
199 #define SMM_SUSP_EN_SET (1 << 1)
200 #define NEST_SMI_EN_SET (1 << 2)
201 #define SMM_INST_EN_SET (1 << 3)
202 #define INTL_SMI_EN_SET (1 << 4)
203 #define EXTL_SMI_EN_SET (1 << 5)
205 #define CPU_EX_BIST 0x1428
208 #define CPU_IM_CONFIG 0x1700
209 #define IM_CONFIG_LOWER_SERIAL_SET (1 << 2)
210 #define IM_CONFIG_LOWER_L0WE_SET (1 << 6)
211 #define IM_CONFIG_LOWER_ICD_SET (1 << 8)
212 #define IM_CONFIG_LOWER_EBE_SET (1 << 10)
213 #define IM_CONFIG_LOWER_ABSE_SET (1 << 11)
214 #define IM_CONFIG_LOWER_QWT_SET (1 << 20)
215 #define CPU_IC_INDEX 0x1710
216 #define CPU_IC_DATA 0x1711
217 #define CPU_IC_TAG 0x1712
218 #define CPU_IC_TAG_I 0x1713
219 #define CPU_ITB_INDEX 0x1720
220 #define CPU_ITB_LRU 0x1721
221 #define CPU_ITB_ENTRY 0x1722
222 #define CPU_ITB_ENTRY_I 0x1723
223 #define CPU_IM_BIST_TAG 0x1730
224 #define CPU_IM_BIST_DATA 0x1731
228 #define CPU_DM_CONFIG0 0x1800
229 #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
230 #define DM_CONFIG0_LOWER_EVCTONRPL_SET (1 << 14)
231 #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
232 #define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8)
233 #define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
235 #define CPU_RCONF_DEFAULT 0x1808
236 #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
237 #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4
238 #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0
239 #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28
240 #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
241 #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
243 #define CPU_RCONF_BYPASS 0x180A
244 #define CPU_RCONF_A0_BF 0x180B
245 #define CPU_RCONF_C0_DF 0x180C
246 #define CPU_RCONF_E0_FF 0x180D
248 #define CPU_RCONF_SMM 0x180E
249 #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
250 #define RCONF_SMM_UPPER_RCSMM_SHIFT 0
251 #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12
252 #define RCONF_SMM_LOWER_RCNORM_SHIFT 0
253 #define RCONF_SMM_LOWER_EN_SET (1<<8)
255 #define CPU_RCONF_DMM 0x180F
256 #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
257 #define RCONF_DMM_UPPER_RCDMM_SHIFT 0
258 #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12
259 #define RCONF_DMM_LOWER_RCNORM_SHIFT 0
260 #define RCONF_DMM_LOWER_EN_SET (1<<8)
262 #define CPU_RCONF0 0x1810
263 #define CPU_RCONF1 0x1811
264 #define CPU_RCONF2 0x1812
265 #define CPU_RCONF3 0x1813
266 #define CPU_RCONF4 0x1814
267 #define CPU_RCONF5 0x1815
268 #define CPU_RCONF6 0x1816
269 #define CPU_RCONF7 0x1817
270 #define CPU_CR1_MSR 0x1881
271 #define CPU_CR2_MSR 0x1882
272 #define CPU_CR3_MSR 0x1883
273 #define CPU_CR4_MSR 0x1884
274 #define CPU_DC_INDEX 0x1890
275 #define CPU_DC_DATA 0x1891
276 #define CPU_DC_TAG 0x1892
277 #define CPU_DC_TAG_I 0x1893
278 #define CPU_SNOOP 0x1894
279 #define CPU_DTB_INDEX 0x1898
280 #define CPU_DTB_LRU 0x1899
281 #define CPU_DTB_ENTRY 0x189A
282 #define CPU_DTB_ENTRY_I 0x189B
283 #define CPU_L2TB_INDEX 0x189C
284 #define CPU_L2TB_LRU 0x189D
285 #define CPU_L2TB_ENTRY 0x189E
286 #define CPU_L2TB_ENTRY_I 0x189F
287 #define CPU_DM_BIST 0x18C0
289 #define CPU_BC_CONF_0 0x1900
290 #define TSC_SUSP_SET (1<<5)
291 #define SUSP_EN_SET (1<<12)
293 #define CPU_BC_CONF_1 0x1901
294 #define CPU_BC_MSR_LOCK 0x1908
295 #define CPU_BC_L2_CONF 0x1920
296 #define BC_L2_ENABLE_SET (1 << 0)
297 #define BC_L2_ALLOC_ENABLE_SET (1 << 1)
298 #define BC_L2_DM_ALLOC_ENABLE_SET (1 << 2)
299 #define BC_L2_IM_ALLOC_ENABLE_SET (1 << 3)
300 #define BC_L2_INVALIDATE_SET (1 << 4)
301 #define CPU_BC_L2_STATUS 0x1921
302 #define CPU_BC_L2_INDEX 0x1922
303 #define CPU_BC_L2_DATA 0x1923
304 #define CPU_BC_L2_TAG 0x1924
305 #define CPU_BC_L2_TAG_AUTOINC 0x1925
306 #define CPU_BC_L2_BIST 0x1926
307 #define BC_L2_BIST_TAG_ENABLE_SET (1 << 0)
308 #define BC_L2_BIST_TAG_DRT_EN_SET (1 << 1)
309 #define BC_L2_BIST_DATA_ENABLE_SET (1 << 2)
310 #define BC_L2_BIST_DATA_DRT_EN_SET (1 << 3)
311 #define BC_L2_BIST_MRU_ENABLE_SET (1 << 4)
312 #define BC_L2_BIST_MRU_DRT_EN_SET (1 << 5)
313 #define CPU_BC_PMODE_MSR 0x1930
314 #define CPU_BC_MSS_ARRAY_CTL_ENA 0x1980
315 #define CPU_BC_MSS_ARRAY_CTL0 0x1981
316 #define CPU_BC_MSS_ARRAY_CTL1 0x1982
317 #define CPU_BC_MSS_ARRAY_CTL2 0x1983
319 #define CPU_FPU_MSR_MODE 0x1A00
320 #define FPU_IE_SET (1 << 0)
322 #define CPU_FP_UROM_BIST 0x1A03
324 #define CPU_CPUID0 0x3000
325 #define CPU_CPUID1 0x3001
326 #define CPU_CPUID2 0x3002
327 #define CPU_CPUID3 0x3003
328 #define CPU_CPUID4 0x3004
329 #define CPU_CPUID5 0x3005
330 #define CPU_CPUID6 0x3006
331 #define CPU_CPUID7 0x3007
332 #define CPU_CPUID8 0x3008
333 #define CPU_CPUID9 0x3009
334 #define CPU_CPUIDA 0x300A
335 #define CPU_CPUIDB 0x300B
336 #define CPU_CPUIDC 0x300C
337 #define CPU_CPUIDD 0x300D
338 #define CPU_CPUIDE 0x300E
339 #define CPU_CPUIDF 0x300F
340 #define CPU_CPUID10 0x3010
341 #define CPU_CPUID11 0x3011
342 #define CPU_CPUID12 0x3012
343 #define CPU_CPUID13 0x3013
351 #define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
352 #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
353 #define VG_GLD_MSR_PM (MSR_VG + 0x2004)
354 #define VG_BIST (MSR_VG + 0x2010)
361 #define GP_GLD_MSR_CAP (MSR_GP + 0x2000)
362 #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
363 #define GP_GLD_MSR_PM (MSR_GP + 0x2004)
370 #define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
371 #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
372 #define DF_LOWER_LCD_SHIFT 6
373 #define DF_GLD_MSR_PM (MSR_DF + 0x2004)
374 #define DF_BIST (MSR_DF + 0x2005)
378 /* GeodeLink Control Processor GLIU1 port3*/
380 #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
381 #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
382 #define GLCP_GLD_MSR_SMI (MSR_GLCP + 0x2002)
383 #define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003)
384 #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
386 #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
387 #define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */
388 #define RSTPLL_UPPER_GLMULT_SHIFT 7
389 #define RSTPLL_UPPER_GLDIV_SHIFT 6
390 #define RSTPLL_UPPER_CPUMULT_SHIFT 1
391 #define RSTPLL_UPPER_CPUDIV_SHIFT 0
392 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26
393 #define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
394 #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
395 #define RSTPPL_LOWER_COREBYPASS_SHIFT 12
396 #define RSTPPL_LOWER_GLBYPASS_SHIFT 11
397 #define RSTPPL_LOWER_PCISPEED_SHIFT 7
398 #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1
399 #define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
401 #define RSTPPL_LOWER_GLLOCK_SET (1 << 25)
402 #define RSTPPL_LOWER_CORELOCK_SET (1 << 24)
403 #define RSTPPL_LOWER_LOCKWAIT_SET (1 << 15)
404 #define RSTPPL_LOWER_CLPD_SET (1 << 14)
405 #define RSTPPL_LOWER_COREPD_SET (1 << 13)
406 #define RSTPPL_LOWER_MBBYPASS_SET (1 << 12)
407 #define RSTPPL_LOWER_COREBYPASS_SET (1 << 11)
408 #define RSTPPL_LOWER_LPFEN_SET (1 << 10)
409 #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
410 #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
411 #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
413 #define GLCP_DOWSER (MSR_GLCP + 0x0E)
414 #define GLCP_DBGCLKCTL (MSR_GLCP + 0x16)
415 #define GLCP_REVID (MSR_GLCP + 0x17)
416 #define GLCP_TH_OD (MSR_GLCP + 0x1E)
417 #define GLCP_FIFOCTL (MSR_GLCP + 0x5E)
418 #define GLCP_BIST GLCP_FIFOCTL
420 #define MSR_INIT (MSR_GLCP + 0x33)
425 #define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
426 #define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
427 #define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
429 #define GLPCI_CTRL (MSR_PCI + 0x2010)
430 #define GLPCI_CTRL_UPPER_FTH_SHIFT 28
431 #define GLPCI_CTRL_UPPER_RTH_SHIFT 24
432 #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
433 #define GLPCI_CTRL_UPPER_RTL_SHIFT 17
434 #define GLPCI_CTRL_UPPER_DTL_SHIFT 14
435 #define GLPCI_CTRL_UPPER_WTO_SHIFT 11
436 #define GLPCI_CTRL_UPPER_SLTO_SHIFT 10
437 #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
438 #define GLPCI_CTRL_UPPER_LAT_SHIFT 3
440 #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
441 #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
442 #define GLPCI_CTRL_LOWER_ER_SET (1<<11)
443 #define GLPCI_CTRL_LOWER_LDE_SET (1<<9)
444 #define GLPCI_CTRL_LOWER_OWC_SET (1<<4)
445 #define GLPCI_CTRL_LOWER_IWC_SET (1<<3)
446 #define GLPCI_CTRL_LOWER_PCD_SET (1<<2)
447 #define GLPCI_CTRL_LOWER_ME_SET (1<<0)
449 #define GLPCI_ARB (MSR_PCI + 0x2011)
450 #define GLPCI_ARB_UPPER_CR_SHIFT 28
451 #define GLPCI_ARB_UPPER_R2_SHIFT 24
452 #define GLPCI_ARB_UPPER_R1_SHIFT 20
453 #define GLPCI_ARB_UPPER_R0_SHIFT 16
454 #define GLPCI_ARB_UPPER_CH_SHIFT 12
455 #define GLPCI_ARB_UPPER_H2_SHIFT 8
456 #define GLPCI_ARB_UPPER_H1_SHIFT 4
457 #define GLPCI_ARB_UPPER_H0_SHIFT 0
459 #define GLPCI_ARB_LOWER_COV_SET (1<<23)
460 #define GLPCI_ARB_LOWER_VO2_SET (1 << 22)
461 #define GLPCI_ARB_LOWER_OV1_SET (1 << 21)
462 #define GLPCI_ARB_LOWER_OV0_SET (1 << 20)
463 #define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
464 #define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
465 #define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
466 #define GLPCI_ARB_LOWER_CPRE_SET (1<<11)
467 #define GLPCI_ARB_LOWER_PRE2_SET (1<<10)
468 #define GLPCI_ARB_LOWER_PRE1_SET (1<<9)
469 #define GLPCI_ARB_LOWER_PRE0_SET (1<<8)
470 #define GLPCI_ARB_LOWER_BM1_SET (1<<7)
471 #define GLPCI_ARB_LOWER_BM0_SET (1<<6)
472 #define GLPCI_ARB_LOWER_EA_SET (1 << 2)
473 #define GLPCI_ARB_LOWER_BMD_SET (1 << 1)
474 #define GLPCI_ARB_LOWER_PARK_SET (1<<0)
476 #define GLPCI_REN (MSR_PCI + 0x2014)
477 #define GLPCI_A0_BF (MSR_PCI + 0x2015)
478 #define GLPCI_C0_DF (MSR_PCI + 0x2016)
479 #define GLPCI_E0_FF (MSR_PCI + 0x2017)
480 #define GLPCI_RC0 (MSR_PCI + 0x2018)
481 #define GLPCI_RC1 (MSR_PCI + 0x2019)
482 #define GLPCI_RC2 (MSR_PCI + 0x201A)
483 #define GLPCI_RC3 (MSR_PCI + 0x201B)
484 #define GLPCI_RC4 (MSR_PCI + 0x201C)
485 #define GLPCI_RC_UPPER_TOP_SHIFT 12
486 #define GLPCI_RC_LOWER_BASE_SHIFT 12
487 #define GLPCI_RC_LOWER_EN_SET (1<<8)
488 #define GLPCI_RC_LOWER_PF_SET (1<<5)
489 #define GLPCI_RC_LOWER_WC_SET (1<<4)
490 #define GLPCI_RC_LOWER_WP_SET (1<<2)
491 #define GLPCI_RC_LOWER_CD_SET (1<<0)
493 #define GLPCI_ExtMSR (MSR_PCI + 0x201E)
495 #define GLPCI_SPARE (MSR_PCI + 0x201F)
496 #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
497 #define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
498 #define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
499 #define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
500 #define GLPCI_SPARE_LOWER_MME_SET (1<<2)
501 #define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
502 #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
506 /* VIP GLIU1 port 5*/
508 #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
509 #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
510 #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
511 #define VIP_BIST (MSR_VIP + 0x2005)
513 /* AES GLIU1 port 6*/
515 #define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
516 #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
517 #define AES_GLD_MSR_PM (MSR_AES + 0x2004)
518 #define AES_CONTROL (MSR_AES + 0x2006)
522 #define MIN_MOD_BANKS 1
523 #define MAX_MOD_BANKS 2
524 #define MIN_DEV_BANKS 2
525 #define MAX_DEV_BANKS 4
526 #define MAX_COL_ADDR 17
529 #define BM 1 /* Base Mask - map power of 2 size aligned region*/
530 #define BMO 2 /* BM with an offset*/
531 #define R 3 /* Range - 4k range minimum*/
532 #define RO 4 /* R with offset*/
533 #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
534 #define BMIO 6 /* Base Mask IO*/
535 #define SCIO 7 /* Swiss 0xCeese IO*/
536 #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU*/
537 #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU*/
538 #define BMO_SMM 10 /* Specail marker for SMM*/
539 #define BM_SMM 11 /* Specail marker for SMM*/
540 #define BMO_DMM 12 /* Specail marker for DMM*/
541 #define BM_DMM 13 /* Specail marker for DMM*/
542 #define RO_FB 14 /* special for Frame buffer.*/
543 #define R_FB 15 /* special for FB.*/
544 #define OTHER 0x0FE /* Special marker for other*/
545 #define GL_END 0x0FF /* end*/
547 #define MSR_GL0 (GL1_GLIU0 << 29)
550 /* Platform stuff but unlikely to change */
551 /* Set up desc addresses from 20 - 3f*/
552 /* This is chip specific!*/
553 #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM*/
554 #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM*/
555 #define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM*/
556 #define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* BM*/
557 #define MSR_GLIU0_BASE5 (MSR_GLIU0 + 0x24) /* BM*/
558 #define MSR_GLIU0_BASE6 (MSR_GLIU0 + 0x25) /* BM*/
560 #define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26)
561 #define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27)
563 #define MSR_GLIU0_SMM (GLIU0_P2D_BMO_0)
564 #define MSR_GLIU0_DMM (GLIU0_P2D_BMO_1)
566 #define GLIU0_P2D_R (MSR_GLIU0 + 0x28)
567 #define MSR_GLIU0_SYSMEM (GLIU0_P2D_R)
569 #define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29)
570 #define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A)
571 #define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
573 #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
575 #define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
576 #define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
577 #define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2)
579 #define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3)
580 #define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4)
581 #define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5)
582 #define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6)
583 #define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7)
584 #define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8)
587 #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM*/
588 #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM*/
589 #define MSR_GLIU1_BASE3 (MSR_GLIU1 + 0x22) /* BM*/
590 #define MSR_GLIU1_BASE4 (MSR_GLIU1 + 0x23) /* BM*/
591 #define MSR_GLIU1_BASE5 (MSR_GLIU1 + 0x24) /* BM*/
592 #define MSR_GLIU1_BASE6 (MSR_GLIU1 + 0x25) /* BM*/
593 #define MSR_GLIU1_BASE7 (MSR_GLIU1 + 0x26) /* BM*/
594 #define MSR_GLIU1_BASE8 (MSR_GLIU1 + 0x27) /* BM*/
595 #define MSR_GLIU1_BASE9 (MSR_GLIU1 + 0x28) /* BM*/
596 #define MSR_GLIU1_BASE10 (MSR_GLIU1 + 0x29) /* BM*/
598 #define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x2A)
599 #define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2B)
600 #define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2C)
601 #define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2D)
604 #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E)
606 #define MSR_GLIU1_SYSMEM (GLIU1_P2D_R_0)
608 #define MSR_GLIU1_SMM (MSR_GLIU1_BASE4) /* BM*/
609 #define MSR_GLIU1_DMM (MSR_GLIU1_BASE5) /* BM*/
611 #define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0)
612 #define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1)
613 #define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2)
615 #define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3)
616 #define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
617 #define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
618 #define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
619 #define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
621 /* ------------------------ */
623 #define SMM_OFFSET 0x80400000 /* above 2GB */
624 #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */