src/include/cpu/amd/gx2def.h

   1 #ifndef CPU_AMD_GX2DEF_H
   2 #define CPU_AMD_GX2DEF_H
   3
   4 /* GeodeLink Control Processor Registers, GLIU1, Port 3 */
   5 #define GLCP_CLK_DIS_DELAY      0x4c000008
   6 #define GLCP_PMCLKDISABLE       0x4c000009
   7 #define GLCP_DELAY_CONTROLS     0x4c00000f
   8 #define GLCP_SYS_RSTPLL         0x4c000014
   9 #define GLCP_DOTPLL             0x4c000015
  10 #define GLCP_CHIP_REVID         0x4c000017
  11
  12 /* GLCP_SYS_RSTPLL, Upper 32 bits */
  13 #define GLCP_SYS_RSTPLL_MDIV_SHIFT   9
  14 #define GLCP_SYS_RSTPLL_VDIV_SHIFT   6
  15 #define GLCP_SYS_RSTPLL_FBDIV_SHIFT  0
  16
  17 /* GLCP_SYS_RSTPLL, Lower 32 bits */
  18 #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT   26
  19 #define GLCP_SYS_RSTPLL_SWFLAGS_MASK    (0x3f << 26)
  20
  21 #define GLCP_SYS_RSTPLL_LOCKWAIT        24
  22 #define GLCP_SYS_RSTPLL_HOLDCOUNT       16
  23 #define GLCP_SYS_RSTPLL_BYPASS          15
  24 #define GLCP_SYS_RSTPLL_PD              14
  25 #define GLCP_SYS_RSTPLL_RESETPLL        13
  26 #define GLCP_SYS_RSTPLL_DDRMODE         10
  27 #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE   9
  28 #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE  8
  29 #define GLCP_SYS_RSTPLL_CHIP_RESET          0
  30
  31 /* MSR routing as follows*/
  32 /* MSB = 1 means not for CPU*/
  33 /* next 3 bits 1st port*/
  34 /* next3 bits next port if through an GLIU*/
  35 /* etc...*/
  36
  37 /*Redcloud as follows.*/
  38 /* GLIU0*/
  39 /*      port0 - GLIU0*/
  40 /*      port1 - MC*/
  41 /*      port2 - GLIU1*/
  42 /*      port3 - CPU*/
  43 /*      port4 - VG*/
  44 /*      port5 - GP*/
  45 /*      port6 - DF*/
  46
  47 /* GLIU1*/
  48 /*      port1 - GLIU0*/
  49 /*      port3 - GLCP*/
  50 /*      port4 - PCI*/
  51 /*      port5 - FG*/
  52
  53
  54 #define GL0_GLIU0                       0
  55 #define GL0_MC                          1
  56 #define GL0_GLIU1                       2
  57 #define GL0_CPU                         3
  58 #define GL0_VG                          4
  59 #define GL0_GP                          5
  60 #define GL0_DF                          6
  61
  62 #define GL1_GLIU0                       1
  63 #define GL1_GLCP                                3
  64 #define GL1_PCI                         4
  65 #define GL1_FG                          5
  66
  67
  68 #define MSR_GLIU0                       (GL0_GLIU0 << 29) + 1 << 28 /* To get on GeodeLink one bit has to be set */
  69 #define MSR_MC                          GL0_MC          << 29
  70 #define MSR_GLIU1                       GL0_GLIU1       << 29
  71 #define MSR_CPU                         GL0_CPU << 29 /* this is not used for BIOS since code executing on CPU doesn't need to be routed*/
  72 #define MSR_VG                          GL0_VG          << 29
  73 #define MSR_GP                          GL0_GP          << 29
  74 #define MSR_DF                          GL0_DF          << 29
  75
  76 #define MSR_GLCP                                (GL1_GLCP << 26) + MSR_GLIU1
  77 #define MSR_PCI                         (GL1_PCI << 26) + MSR_GLIU1
  78 #define MSR_FG                          (GL1_FG << 26) + MSR_GLIU1
  79
  80 /* South Bridge*/
  81 #define MSR_SB                          (SB_PORT << 23) + MSR_PCI       /* address to the SouthBridge*/
  82 #define SB_SHIFT                        20                                                      /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/
  83
  84
  85 /**/
  86 /*GeodeLink Interface Unit 0 (GLIU0) port0*/
  87 /**/
  88
  89 #define GLIU0_GLD_MSR_CAP                       MSR_GLIU0 + 2000h
  90 #define GLIU0_GLD_MSR_PM                        MSR_GLIU0 + 2004h
  91
  92 #define GLIU0_DESC_BASE                         MSR_GLIU0 + 20h
  93 #define GLIU0_CAP                                       MSR_GLIU0 + 86h
  94 #define GLIU0_GLD_MSR_COH                       MSR_GLIU0 + 80h
  95
  96
  97 /**/
  98 /* Memory Controller GLIU0 port 1*/
  99 /**/
 100 #define MC_GLD_MSR_CAP                  MSR_MC + 2000h
 101 #define MC_GLD_MSR_PM                   MSR_MC + 2004h
 102
 103 #define MC_CF07_DATA                    MSR_MC + 18h
 104
 105 #define         CF07_UPPER_D1_SZ_SHIFT                          28
 106 #define         CF07_UPPER_D1_MB_SHIFT                          24
 107 #define         CF07_UPPER_D1_CB_SHIFT                          20
 108 #define         CF07_UPPER_D1_PSZ_SHIFT                         16
 109 #define         CF07_UPPER_D0_SZ_SHIFT                          12
 110 #define         CF07_UPPER_D0_MB_SHIFT                          8
 111 #define         CF07_UPPER_D0_CB_SHIFT                          4
 112 #define         CF07_UPPER_D0_PSZ_SHIFT                         0
 113
 114 #define         CF07_LOWER_REF_INT_SHIFT                        8
 115 #define         CF07_LOWER_LOAD_MODE_DDR_SET                    01 << 28
 116 #define         CF07_LOWER_LOAD_MODE_DLL_RESET                  01 << 27
 117 #define         CF07_LOWER_EMR_QFC_SET                          01 << 26
 118 #define         CF07_LOWER_EMR_DRV_SET                          01 << 25
 119 #define         CF07_LOWER_REF_TEST_SET                         1 << 3
 120 #define         CF07_LOWER_PROG_DRAM_SET                        1 << 0
 121
 122
 123 #define MC_CF8F_DATA                    MSR_MC + 19h
 124
 125 #define         CF8F_UPPER_XOR_BS_SHIFT                         19
 126 #define         CF8F_UPPER_XOR_MB0_SHIFT                        18
 127 #define         CF8F_UPPER_XOR_BA1_SHIFT                        17
 128 #define         CF8F_UPPER_XOR_BA0_SHIFT                        16
 129 #define         CF8F_UPPER_REORDER_DIS_SET                      1 << 8
 130 #define         CF8F_UPPER_REG_DIMM_SHIFT                       4
 131 #define         CF8F_LOWER_CAS_LAT_SHIFT                        28
 132 #define         CF8F_LOWER_REF2ACT_SHIFT                        24
 133 #define         CF8F_LOWER_ACT2PRE_SHIFT                        20
 134 #define         CF8F_LOWER_PRE2ACT_SHIFT                        16
 135 #define         CF8F_LOWER_ACT2CMD_SHIFT                        12
 136 #define         CF8F_LOWER_ACT2ACT_SHIFT                        8
 137 #define         CF8F_UPPER_32BIT_SET                            1 << 5
 138 #define         CF8F_UPPER_HOI_LOI_SET                          1 << 1
 139
 140 #define MC_CF1017_DATA                  MSR_MC + 1Ah
 141
 142 #define         CF1017_LOWER_PM1_UP_DLY_SET                                     1 << 8
 143 #define         CF1017_LOWER_WR2DAT_SHIFT                                       0
 144
 145 #define MC_CFCLK_DBUG                   MSR_MC + 1Dh
 146
 147 #define         CFCLK_UPPER_MTST_B2B_DIS_SET                    1 << 2
 148 #define         CFCLK_UPPER_MTST_DQS_EN_SET                     1 << 1
 149 #define         CFCLK_UPPER_MTEST_EN_SET                        1 << 0
 150
 151 #define         CFCLK_LOWER_MASK_CKE_SET1                       1 << 9
 152 #define         CFCLK_LOWER_MASK_CKE_SET0                       1 << 8
 153 #define         CFCLK_LOWER_SDCLK_SET                           0Fh << 0
 154
 155 #define MC_CF_RDSYNC             MSR_MC + 1Fh
 156
 157
 158 /**/
 159 /* GLIU1 GLIU0 port2*/
 160 /**/
 161 #define GLIU1_GLD_MSR_CAP                       MSR_GLIU1 + 2000h
 162 #define GLIU1_GLD_MSR_PM                        MSR_GLIU1 + 2004h
 163
 164 #define GLIU1_GLD_MSR_COH                       MSR_GLIU1 + 80h
 165
 166
 167 /**/
 168 /* CPU  ; does not need routing instructions since we are executing there.*/
 169 /**/
 170 #define CPU_GLD_MSR_CAP                                         2000h
 171 #define CPU_GLD_MSR_CONFIG                                      2001h
 172 #define CPU_GLD_MSR_PM                                          2004h
 173
 174 #define CPU_GLD_MSR_DIAG                                        2005h
 175 #define         DIAG_SEL1_MODE_SHIFT                            16
 176 #define         DIAG_SEL1_SET                                           1 << 31
 177 #define         DIAG_SEL0__MODE_SHIFT                           0
 178 #define         DIAG_SET0_SET                                           1 << 15
 179
 180 #define CPU_PF_BTB_CONF                                         1100h
 181 #define         BTB_ENABLE_SET                                          1 << 0
 182 #define         RETURN_STACK_ENABLE_SET                         1 << 4
 183 #define CPU_PF_BTBRMA_BIST                                      110Ch
 184
 185 #define CPU_XC_CONFIG                                           1210h
 186 #define         XC_CONFIG_SUSP_ON_HLT                           1 << 0
 187 #define CPU_ID_CONFIG                                           1250h
 188 #define         ID_CONFIG_SERIAL_SET                            1 << 0
 189
 190 #define CPU_AC_MSR                                                      1301h
 191 #define CPU_EX_BIST                                                     1428h
 192
 193 /*IM*/
 194 #define CPU_IM_CONFIG                                                   1700h
 195 #define         IM_CONFIG_LOWER_ICD_SET                                 1 << 8
 196 #define         IM_CONFIG_LOWER_QWT_SET                                 1 << 20
 197 #define CPU_IC_INDEX                                                    1710h
 198 #define CPU_IC_DATA                                                             1711h
 199 #define CPU_IC_TAG                                                              1712h
 200 #define CPU_IC_TAG_I                                                    1713h
 201 #define CPU_ITB_INDEX                                                   1720h
 202 #define CPU_ITB_LRU                                                             1721h
 203 #define CPU_ITB_ENTRY                                                   1722h
 204 #define CPU_ITB_ENTRY_I                                                 1723h
 205 #define CPU_IM_BIST_TAG                                                 1730h
 206 #define CPU_IM_BIST_DATA                                                1731h
 207
 208
 209 /* various CPU MSRs */
 210 #define CPU_DM_CONFIG0 0x1800
 211 #define DM_CONFIG0_UPPER_WSREQ_SHIFT  12
 212 #define DM_CONFIG0_LOWER_DCDIS_SET              (1<<8)
 213 #define DM_CONFIG0_LOWER_WBINVD_SET     (1<<5)
 214 #define DM_CONFIG0_LOWER_MISSER_SET             (1<<1)
 215 /* configuration MSRs */
 216 #define CPU_RCONF_DEFAULT                                               0x1808
 217 #define         RCONF_DEFAULT_UPPER_ROMRC_SHIFT                         24
 218 #define         RCONF_DEFAULT_UPPER_ROMBASE_SHIFT                       4
 219 #define         RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT                      0
 220 #define         RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT                     28
 221 #define         RCONF_DEFAULT_LOWER_SYSTOP_SHIFT                        8
 222 #define         RCONF_DEFAULT_LOWER_SYSRC_SHIFT                         0
 223
 224 #define CPU_RCONF_BYPASS                                                0x180A
 225 #define CPU_RCONF_A0_BF                                                 0x180B
 226 #define CPU_RCONF_C0_DF                                                 0x180C
 227 #define CPU_RCONF_E0_FF                                                 0x180D
 228
 229 #define CPU_RCONF_SMM                                                   0x180E
 230 #define         RCONF_SMM_UPPER_SMMTOP_SHIFT                    12
 231 #define         RCONF_SMM_UPPER_RCSMM_SHIFT                             0
 232 #define         RCONF_SMM_LOWER_SMMBASE_SHIFT                   12
 233 #define         RCONF_SMM_LOWER_RCNORM_SHIFT                    0
 234 #define         RCONF_SMM_LOWER_EN_SET                                  (1<<8)
 235
 236 #define CPU_RCONF_DMM                                                   0x180F
 237 #define         RCONF_DMM_UPPER_DMMTOP_SHIFT                    12
 238 #define         RCONF_DMM_UPPER_RCDMM_SHIFT                             0
 239 #define         RCONF_DMM_LOWER_DMMBASE_SHIFT                   12
 240 #define         RCONF_DMM_LOWER_RCNORM_SHIFT                    0
 241 #define         RCONF_DMM_LOWER_EN_SET                                  (1<<8)
 242
 243 #define CPU_RCONF0                                                      0x1810
 244 #define CPU_RCONF1                                                      0x1811
 245 #define CPU_RCONF2                                                      0x1812
 246 #define CPU_RCONF3                                                      0x1813
 247 #define CPU_RCONF4                                                      0x1814
 248 #define CPU_RCONF5                                                      0x1815
 249 #define CPU_RCONF6                                                      0x1816
 250 #define CPU_RCONF7                                                      0x1817
 251 #define CPU_CR1_MSR                                                     0x1881
 252 #define CPU_CR2_MSR                                                     0x1882
 253 #define CPU_CR3_MSR                                                     0x1883
 254 #define CPU_CR4_MSR                                                     0x1884
 255 #define CPU_DC_INDEX                                            0x1890
 256 #define CPU_DC_DATA                                                     0x1891
 257 #define CPU_DC_TAG                                                      0x1892
 258 #define CPU_DC_TAG_I                                            0x1893
 259 #define CPU_SNOOP                                                       0x1894
 260 #define CPU_DTB_INDEX                                           0x1898
 261 #define CPU_DTB_LRU                                                     0x1899
 262 #define CPU_DTB_ENTRY                                           0x189A
 263 #define CPU_DTB_ENTRY_I                                         0x189B
 264 #define CPU_L2TB_INDEX                                          0x189C
 265 #define CPU_L2TB_LRU                                            0x189D
 266 #define CPU_L2TB_ENTRY                                          0x189E
 267 #define CPU_L2TB_ENTRY_I                                        0x189F
 268 #define CPU_DM_BIST                                                     0x18C0
 269                 /* SMM*/
 270 #define CPU_AC_SMM_CTL                                          0x1301
 271 #define         SMM_NMI_EN_SET                                  (1<<0)
 272 #define         SMM_SUSP_EN_SET                                 (1<<1)
 273 #define         NEST_SMI_EN_SET                                 (1<<2)
 274 #define         SMM_INST_EN_SET                                 (1<<3)
 275 #define         INTL_SMI_EN_SET                                 (1<<4)
 276 #define         EXTL_SMI_EN_SET                                 (1<<5)
 277
 278 #define CPU_FPU_MSR_MODE                                        0x1A00
 279 #define         FPU_IE_SET                                              (1<<0)
 280
 281 #define CPU_FP_UROM_BIST                                        0x1A03
 282
 283 #define CPU_BC_CONF_0                                           0x1900
 284 #define         TSC_SUSP_SET                             (1<<5)
 285 #define         SUSP_EN_SET                              (1<<1)2
 286
 287         /**/
 288         /*      VG GLIU0 port4*/
 289         /**/
 290
 291 #define VG_GLD_MSR_CAP                  MSR_VG + 0x2000
 292 #define VG_GLD_MSR_CONFIG               MSR_VG + 0x2001
 293 #define VG_GLD_MSR_PM                   MSR_VG + 0x2004
 294
 295 #endif /* CPU_AMD_GX2DEF_H */