src/include/cpu/amd/geode_post_code.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* standard AMD post definitions -- might as well use them. */
  21 #define POST_Output_Port                        (0x080) /*      port to write post codes to*/
  22
  23 #define POST_preSioInit                         (0x000)
  24 #define POST_clockInit                          (0x001)
  25 #define POST_CPURegInit                         (0x002)
  26 #define POST_UNREAL                             (0x003)
  27 #define POST_CPUMemRegInit                      (0x004)
  28 #define POST_CPUTest                            (0x005)
  29 #define POST_memSetup                           (0x006)
  30 #define POST_memSetUpStack                      (0x007)
  31 #define POST_memTest                            (0x008)
  32 #define POST_shadowRom                          (0x009)
  33 #define POST_memRAMoptimize                     (0x00A)
  34 #define POST_cacheInit                          (0x00B)
  35 #define POST_northBridgeInit                    (0x00C)
  36 #define POST_chipsetInit                        (0x00D)
  37 #define POST_sioTest                            (0x00E)
  38 #define POST_pcATjunk                           (0x00F)
  39
  40 #define POST_intTable                           (0x010)
  41 #define POST_memInfo                            (0x011)
  42 #define POST_romCopy                            (0x012)
  43 #define POST_PLLCheck                           (0x013)
  44 #define POST_keyboardInit                       (0x014)
  45 #define POST_cpuCacheOff                        (0x015)
  46 #define POST_BDAInit                            (0x016)
  47 #define POST_pciScan                            (0x017)
  48 #define POST_optionRomInit                      (0x018)
  49 #define POST_ResetLimits                        (0x019)
  50 #define POST_summary_screen                     (0x01A)
  51 #define POST_Boot                               (0x01B)
  52 #define POST_SystemPreInit                      (0x01C)
  53 #define POST_ClearRebootFlag                    (0x01D)
  54 #define POST_GLIUInit                           (0x01E)
  55 #define POST_BootFailed                         (0x01F)
  56
  57 #define POST_CPU_ID                             (0x020)
  58 #define POST_COUNTERBROKEN                      (0x021)
  59 #define POST_DIFF_DIMMS                         (0x022)
  60 #define POST_WIGGLE_MEM_LINES                   (0x023)
  61 #define POST_NO_GLIU_DESC                       (0x024)
  62 #define POST_CPU_LCD_CHECK                      (0x025)
  63 #define POST_CPU_LCD_PASS                       (0x026)
  64 #define POST_CPU_LCD_FAIL                       (0x027)
  65 #define POST_CPU_STEPPING                       (0x028)
  66 #define POST_CPU_DM_BIST_FAILURE                (0x029)
  67 #define POST_CPU_FLAGS                          (0x02A)
  68 #define POST_CHIPSET_ID                         (0x02B)
  69 #define POST_CHIPSET_ID_PASS                    (0x02C)
  70 #define POST_CHIPSET_ID_FAIL                    (0x02D)
  71 #define POST_CPU_ID_GOOD                        (0x02E)
  72 #define POST_CPU_ID_FAIL                        (0x02F)
  73
  74 /*      PCI config*/
  75 #define P80_PCICFG                              (0x030)
  76
  77 /*      PCI io*/
  78 #define P80_PCIIO                               (0x040)
  79
  80 /*      PCI memory*/
  81 #define P80_PCIMEM                              (0x050)
  82
  83 /*      SIO*/
  84 #define P80_SIO                                 (0x060)
  85
  86 /*      Memory Setp*/
  87 #define P80_MEM_SETUP                           (0x070)
  88 #define POST_MEM_SETUP                          (0x070)
  89 #define ERROR_32BIT_DIMMS                       (0x071)
  90 #define POST_MEM_SETUP2                         (0x072)
  91 #define POST_MEM_SETUP3                         (0x073)
  92 #define POST_MEM_SETUP4                         (0x074)
  93 #define POST_MEM_SETUP5                         (0x075)
  94 #define POST_MEM_ENABLE                         (0x076)
  95 #define ERROR_NO_DIMMS                          (0x077)
  96 #define ERROR_DIFF_DIMMS                        (0x078)
  97 #define ERROR_BAD_LATENCY                       (0x079)
  98 #define ERROR_SET_PAGE                          (0x07A)
  99 #define ERROR_DENSITY_DIMM                      (0x07B)
 100 #define ERROR_UNSUPPORTED_DIMM                  (0x07C)
 101 #define ERROR_BANK_SET                          (0x07D)
 102 #define POST_MEM_SETUP_GOOD                     (0x07E)
 103 #define POST_MEM_SETUP_FAIL                     (0x07F)
 104
 105 #define POST_UserPreInit                        (0x080)
 106 #define POST_UserPostInit                       (0x081)
 107 #define POST_Equipment_check                    (0x082)
 108 #define POST_InitNVRAMBX                        (0x083)
 109 #define POST_NoPIRTable                         (0x084)
 110 #define POST_ChipsetFingerPrintPass             (0x085)
 111 #define POST_ChipsetFingerPrintFail             (0x086)
 112 #define POST_CPU_IM_TAG_BIST_FAILURE            (0x087)
 113 #define POST_CPU_IM_DATA_BIST_FAILURE           (0x088)
 114 #define POST_CPU_FPU_BIST_FAILURE               (0x089)
 115 #define POST_CPU_BTB_BIST_FAILURE               (0x08A)
 116 #define POST_CPU_EX_BIST_FAILURE                (0x08B)
 117 #define POST_Chipset_PI_Test_Fail               (0x08C)
 118 #define POST_Chipset_SMBus_SDA_Test_Fail        (0x08D)
 119 #define POST_BIT_CLK_Fail                       (0x08E)
 120
 121 #define POST_STACK_SETUP                        (0x090)
 122 #define POST_CPU_PF_BIST_FAILURE                (0x091)
 123 #define POST_CPU_L2_BIST_FAILURE                (0x092)
 124 #define POST_CPU_GLCP_BIST_FAILURE              (0x093)
 125 #define POST_CPU_DF_BIST_FAILURE                (0x094)
 126 #define POST_CPU_VG_BIST_FAILURE                (0x095)
 127 #define POST_CPU_VIP_BIST_FAILURE               (0x096)
 128 #define POST_STACK_SETUP_PASS                   (0x09E)
 129 #define POST_STACK_SETUP_FAIL                   (0x09F)
 130
 131 #define POST_PLL_INIT                           (0x0A0)
 132 #define POST_PLL_MANUAL                         (0x0A1)
 133 #define POST_PLL_STRAP                          (0x0A2)
 134 #define POST_PLL_RESET_FAIL                     (0x0A3)
 135 #define POST_PLL_PCI_FAIL                       (0x0A4)
 136 #define POST_PLL_MEM_FAIL                       (0x0A5)
 137 #define POST_PLL_CPU_VER_FAIL                   (0x0A6)
 138
 139 #define POST_MEM_TESTMEM                        (0x0B0)
 140 #define POST_MEM_TESTMEM1                       (0x0B1)
 141 #define POST_MEM_TESTMEM2                       (0x0B2)
 142 #define POST_MEM_TESTMEM3                       (0x0B3)
 143 #define POST_MEM_TESTMEM4                       (0x0B4)
 144 #define POST_MEM_TESTMEM_PASS                   (0x0BE)
 145 #define POST_MEM_TESTMEM_FAIL                   (0x0BF)
 146
 147 #define POST_SECUROM_SECBOOT_START              (0x0C0)
 148 #define POST_SECUROM_BOOTSRCSETUP               (0x0C1)
 149 #define POST_SECUROM_REMAP_FAIL                 (0x0C2)
 150 #define POST_SECUROM_BOOTSRCSETUP_FAIL          (0x0C3)
 151 #define POST_SECUROM_DCACHESETUP                (0x0C4)
 152 #define POST_SECUROM_DCACHESETUP_FAIL           (0x0C5)
 153 #define POST_SECUROM_ICACHESETUP                (0x0C6)
 154 #define POST_SECUROM_DESCRIPTORSETUP            (0x0C7)
 155 #define POST_SECUROM_DCACHESETUPBIOS            (0x0C8)
 156 #define POST_SECUROM_PLATFORMSETUP              (0x0C9)
 157 #define POST_SECUROM_SIGCHECKBIOS               (0x0CA)
 158 #define POST_SECUROM_ICACHESETUPBIOS            (0x0CB)
 159 #define POST_SECUROM_PASS                       (0x0CC)
 160 #define POST_SECUROM_FAIL                       (0x0CD)
 161
 162 #define POST_RCONFInitError                     (0x0CE)
 163 #define POST_CacheInitError                     (0x0CF)
 164
 165 #define POST_ROM_PREUNCOMPRESS                  (0x0D0)
 166 #define POST_ROM_UNCOMPRESS                     (0x0D1)
 167 #define POST_ROM_SMM_INIT                       (0x0D2)
 168 #define POST_ROM_VID_BIOS                       (0x0D3)
 169 #define POST_ROM_LCDINIT                        (0x0D4)
 170 #define POST_ROM_SPLASH                         (0x0D5)
 171 #define POST_ROM_HDDINIT                        (0x0D6)
 172 #define POST_ROM_SYS_INIT                       (0x0D7)
 173 #define POST_ROM_DMM_INIT                       (0x0D8)
 174 #define POST_ROM_TVINIT                         (0x0D9)
 175 #define POST_ROM_POSTUNCOMPRESS                 (0x0DE)
 176
 177 #define P80_CHIPSET_INIT                        (0x0E0)
 178 #define POST_PreChipsetInit                     (0x0E1)
 179 #define POST_LateChipsetInit                    (0x0E2)
 180 #define POST_NORTHB_INIT                        (0x0E8)
 181
 182 #define POST_INTR_SEG_JUMP                      (0x0F0)