src/devices/pci_device.c

   1 /*
   2  *      PCI Bus Services, see include/linux/pci.h for further explanation.
   3  *
   4  *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
   5  *      David Mosberger-Tang
   6  *
   7  *      Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
   8  *
   9  *      Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
  10  */
  11
  12 #include <console/console.h>
  13 #include <stdlib.h>
  14 #include <stdint.h>
  15 #include <bitops.h>
  16 #include <string.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20 #include <part/hard_reset.h>
  21 #include <part/fallback_boot.h>
  22
  23 /** Given a device and register, read the size of the BAR for that register.
  24  * @param dev       Pointer to the device structure
  25  * @param resource  Pointer to the resource structure
  26  * @param index     Address of the pci configuration register
  27  */
  28 static void pci_get_resource(struct device *dev, struct resource *resource, unsigned long index)
  29 {
  30         uint32_t addr, size, base;
  31         unsigned long type;
  32
  33         /* Initialize the resources to nothing */
  34         resource->base = 0;
  35         resource->size = 0;
  36         resource->align = 0;
  37         resource->gran = 0;
  38         resource->limit = 0;
  39         resource->flags = 0;
  40         resource->index = index;
  41
  42         addr = pci_read_config32(dev, index);
  43
  44         /* FIXME: more consideration for 64-bit PCI devices,
  45          * we currently detect their size but otherwise
  46          * treat them as 32-bit resources
  47          */
  48         /* get the size */
  49         pci_write_config32(dev, index, ~0);
  50         size = pci_read_config32(dev,  index);
  51
  52         /* get the minimum value the bar can be set to */
  53         pci_write_config32(dev, index, 0);
  54         base = pci_read_config32(dev, index);
  55
  56         /* restore addr */
  57         pci_write_config32(dev, index, addr);
  58
  59         /*
  60          * some broken hardware has read-only registers that do not
  61          * really size correctly. You can tell this if addr == size
  62          * Example: the acer m7229 has BARs 1-4 normally read-only.
  63          * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
  64          * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
  65          * violation of the spec.
  66          * We catch this case and ignore it by settting size and type to 0.
  67          * This incidentally catches the common case where registers
  68          * read back as 0 for both address and size.
  69          */
  70         if ((addr == size) && (addr == base)) {
  71                 if (size != 0) {
  72                         printk_debug(
  73                                 "%s register %02x(%08x), read-only ignoring it\n",
  74                                 dev_path(dev),
  75                                 index, addr);
  76                 }
  77                 resource->flags = 0;
  78         }
  79         /* Now compute the actual size, See PCI Spec 6.2.5.1 ...  */
  80         else if (size & PCI_BASE_ADDRESS_SPACE_IO) {
  81                 type = size & (~PCI_BASE_ADDRESS_IO_MASK);
  82                 /* BUG! Top 16 bits can be zero (or not)
  83                  * So set them to 0xffff so they go away ...
  84                  */
  85                 resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1;
  86                 resource->align = log2(resource->size);
  87                 resource->gran = resource->align;
  88                 resource->flags = IORESOURCE_IO;
  89                 resource->limit = 0xffff;
  90         }
  91         else {
  92                 /* A Memory mapped base address */
  93                 type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
  94                 resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1;
  95                 resource->align = log2(resource->size);
  96                 resource->gran = resource->align;
  97                 resource->flags = IORESOURCE_MEM;
  98                 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
  99                         resource->flags |= IORESOURCE_PREFETCH;
 100                 }
 101                 type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 102                 if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) {
 103                         /* 32bit limit */
 104                         resource->limit = 0xffffffffUL;
 105                 }
 106                 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) {
 107                         /* 1MB limit */
 108                         resource->limit = 0x000fffffUL;
 109                 }
 110                 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
 111                         unsigned long index_hi;
 112                         /* 64bit limit
 113                          * For now just treat this as a 32bit limit
 114                          */
 115                         index_hi = index + 4;
 116                         resource->limit = 0xffffffffUL;
 117                         resource->flags |= IORESOURCE_PCI64;
 118                         addr = pci_read_config32( dev, index_hi);
 119                         /* get the extended size */
 120                         pci_write_config32(dev, index_hi, 0xffffffffUL);
 121                         size = pci_read_config32( dev, index_hi);
 122
 123                         /* get the minimum value the bar can be set to */
 124                         pci_write_config32(dev, index_hi, 0);
 125                         base = pci_read_config32(dev,  index_hi);
 126
 127                         /* restore addr */
 128                         pci_write_config32(dev, index_hi, addr);
 129
 130                         if ((size == 0xffffffff) && (base == 0)) {
 131                                 /* Clear the top half of the bar */
 132                                 pci_write_config32(dev, index_hi, 0);
 133                         }
 134                         else {
 135                                 printk_err("%s Unable to handle 64-bit address\n",
 136                                         dev_path(dev));
 137                                 resource->flags = IORESOURCE_PCI64;
 138                         }
 139                 }
 140                 else {
 141                         /* Invalid value */
 142                         resource->flags = 0;
 143                 }
 144         }
 145         /* dev->size holds the flags... */
 146         return;
 147 }
 148
 149 /** Read the base address registers for a given device.
 150  * @param dev Pointer to the dev structure
 151  * @param howmany How many registers to read (6 for device, 2 for bridge)
 152  */
 153 static void pci_read_bases(struct device *dev, unsigned int howmany)
 154 {
 155         unsigned int reg;
 156         unsigned long index;
 157
 158         reg = dev->resources;
 159         for(index = PCI_BASE_ADDRESS_0;
 160             (reg < MAX_RESOURCES) && (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
 161                 struct resource *resource;
 162                 resource = &dev->resource[reg];
 163                 pci_get_resource(dev, resource, index);
 164                 reg += (resource->flags & (IORESOURCE_IO | IORESOURCE_MEM))? 1:0;
 165                 index += (resource->flags & IORESOURCE_PCI64)?8:4;
 166         }
 167         dev->resources = reg;
 168 }
 169
 170
 171 static void pci_bridge_read_bases(struct device *dev)
 172 {
 173         unsigned int reg = dev->resources;
 174
 175         /* FIXME handle bridges without some of the optional resources */
 176
 177         /* Initialize the io space constraints on the current bus */
 178         dev->resource[reg].base  = 0;
 179         dev->resource[reg].size  = 0;
 180         dev->resource[reg].align = log2(PCI_IO_BRIDGE_ALIGN);
 181         dev->resource[reg].gran  = log2(PCI_IO_BRIDGE_ALIGN);
 182         dev->resource[reg].limit = 0xffffUL;
 183         dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_PCI_BRIDGE;
 184         dev->resource[reg].index = PCI_IO_BASE;
 185         compute_allocate_resource(&dev->link[0], &dev->resource[reg],
 186                 IORESOURCE_IO, IORESOURCE_IO);
 187         reg++;
 188
 189         /* Initiliaze the prefetchable memory constraints on the current bus */
 190         dev->resource[reg].base = 0;
 191         dev->resource[reg].size = 0;
 192         dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
 193         dev->resource[reg].gran  = log2(PCI_MEM_BRIDGE_ALIGN);
 194         dev->resource[reg].limit = 0xffffffffUL;
 195         dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE;
 196         dev->resource[reg].index = PCI_PREF_MEMORY_BASE;
 197         compute_allocate_resource(&dev->link[0], &dev->resource[reg],
 198                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 199                 IORESOURCE_MEM | IORESOURCE_PREFETCH);
 200         reg++;
 201
 202         /* Initialize the memory resources on the current bus */
 203         dev->resource[reg].base = 0;
 204         dev->resource[reg].size = 0;
 205         dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
 206         dev->resource[reg].gran  = log2(PCI_MEM_BRIDGE_ALIGN);
 207         dev->resource[reg].limit = 0xffffffffUL;
 208         dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE;
 209         dev->resource[reg].index = PCI_MEMORY_BASE;
 210         compute_allocate_resource(&dev->link[0], &dev->resource[reg],
 211                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 212                 IORESOURCE_MEM);
 213         reg++;
 214
 215         dev->resources = reg;
 216 }
 217
 218
 219 void pci_dev_read_resources(struct device *dev)
 220 {
 221         uint32_t addr;
 222         dev->resources = 0;
 223         memset(&dev->resource[0], 0, sizeof(dev->resource));
 224         pci_read_bases(dev, 6);
 225         addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
 226         dev->rom_address = (addr == 0xffffffff)? 0 : addr;
 227 }
 228
 229 void pci_bus_read_resources(struct device *dev)
 230 {
 231         uint32_t addr;
 232         dev->resources = 0;
 233         memset(&dev->resource, 0, sizeof(dev->resource));
 234         pci_bridge_read_bases(dev);
 235         pci_read_bases(dev, 2);
 236
 237         addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
 238         dev->rom_address = (addr == 0xffffffff)? 0 : addr;
 239
 240 }
 241
 242
 243 static void pci_set_resource(struct device *dev, struct resource *resource)
 244 {
 245         unsigned long base, limit;
 246         unsigned char buf[10];
 247         unsigned long align;
 248
 249         /* Make certain the resource has actually been set */
 250         if (!(resource->flags & IORESOURCE_SET)) {
 251 #if 1
 252                 printk_err("ERROR: %s %02x not allocated\n",
 253                         dev_path(dev), resource->index);
 254 #endif
 255                 return;
 256         }
 257
 258         /* Only handle PCI memory and IO resources for now */
 259         if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
 260                 return;
 261
 262         if (resource->flags & IORESOURCE_MEM) {
 263                 dev->command |= PCI_COMMAND_MEMORY;
 264         }
 265         if (resource->flags & IORESOURCE_IO) {
 266                 dev->command |= PCI_COMMAND_IO;
 267         }
 268         if (resource->flags & IORESOURCE_PCI_BRIDGE) {
 269                 dev->command |= PCI_COMMAND_MASTER;
 270         }
 271         /* Get the base address */
 272         base = resource->base;
 273         /* Get the resource alignment */
 274         align = 1UL << resource->align;
 275
 276         /* Get the limit (rounded up) */
 277         limit = base + ((resource->size + align - 1UL) & ~(align - 1UL)) -1UL;
 278
 279         if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 280                 /*
 281                  * some chipsets allow us to set/clear the IO bit.
 282                  * (e.g. VIA 82c686a.) So set it to be safe)
 283                  */
 284                 limit = base + resource->size -1;
 285                 if (resource->flags & IORESOURCE_IO) {
 286                         base |= PCI_BASE_ADDRESS_SPACE_IO;
 287                 }
 288                 pci_write_config32(dev, resource->index, base & 0xffffffff);
 289                 if (resource->flags & IORESOURCE_PCI64) {
 290                         /* FIXME handle real 64bit base addresses */
 291                         pci_write_config32(dev, resource->index + 4, 0);
 292                 }
 293         }
 294         else if (resource->index == PCI_IO_BASE) {
 295                 /* set the IO ranges
 296                  * WARNING: we don't really do 32-bit addressing for IO yet!
 297                  */
 298                 compute_allocate_resource(&dev->link[0], resource,
 299                         IORESOURCE_IO, IORESOURCE_IO);
 300                 pci_write_config8(dev, PCI_IO_BASE,  base >> 8);
 301                 pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
 302                 pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0);
 303                 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0);
 304         }
 305         else if (resource->index == PCI_MEMORY_BASE) {
 306                 /* set the memory range
 307                  */
 308                 compute_allocate_resource(&dev->link[0], resource,
 309                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 310                         IORESOURCE_MEM);
 311                 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
 312                 pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
 313         }
 314         else if (resource->index == PCI_PREF_MEMORY_BASE) {
 315                 /* set the prefetchable memory range
 316                  * WARNING: we don't really do 64-bit addressing for prefetchable memory yet!
 317                  */
 318                 compute_allocate_resource(&dev->link[0], resource,
 319                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 320                         IORESOURCE_MEM | IORESOURCE_PREFETCH);
 321                 pci_write_config16(dev, PCI_PREF_MEMORY_BASE,  base >> 16);
 322                 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
 323                 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0);
 324                 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0);
 325         }
 326         else {
 327                 printk_err("ERROR: invalid resource->index %x\n",
 328                         resource->index);
 329         }
 330         buf[0] = '\0';
 331         if (resource->flags & IORESOURCE_PCI_BRIDGE) {
 332                 sprintf(buf, "bus %d ", dev->link[0].secondary);
 333         }
 334
 335         printk_debug(
 336                 "%s %02x <- [0x%08lx - 0x%08lx] %s%s\n",
 337                 dev_path(dev),
 338                 resource->index,
 339                 resource->base, limit,
 340                 buf,
 341                 (resource->flags & IORESOURCE_IO)? "io":
 342                 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
 343         return;
 344 }
 345
 346 void pci_dev_set_resources(struct device *dev)
 347 {
 348         struct resource *resource, *last;
 349         unsigned link;
 350         uint8_t line;
 351
 352         last = &dev->resource[dev->resources];
 353
 354         for(resource = &dev->resource[0]; resource < last; resource++) {
 355                 pci_set_resource(dev, resource);
 356         }
 357         for(link = 0; link < dev->links; link++) {
 358                 struct bus *bus;
 359                 bus = &dev->link[link];
 360                 if (bus->children) {
 361                         assign_resources(bus);
 362                 }
 363         }
 364
 365         /* set a default latency timer */
 366         pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 367
 368         /* set a default secondary latency timer */
 369         if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
 370                 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
 371         }
 372
 373         /* zero the irq settings */
 374         line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
 375         if (line) {
 376                 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 377         }
 378         /* set the cache line size, so far 64 bytes is good for everyone */
 379         pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 380 }
 381
 382 void pci_dev_enable_resources(struct device *dev)
 383 {
 384         uint16_t command;
 385         command = pci_read_config16(dev, PCI_COMMAND);
 386         command |= dev->command;
 387         printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
 388         pci_write_config16(dev, PCI_COMMAND, command);
 389
 390         enable_childrens_resources(dev);
 391 }
 392
 393 void pci_bus_enable_resources(struct device *dev)
 394 {
 395         uint16_t ctrl;
 396         ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 397         ctrl |= dev->link[0].bridge_ctrl;
 398         printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
 399         pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 400
 401         pci_dev_enable_resources(dev);
 402 }
 403
 404 struct device_operations default_pci_ops_dev = {
 405         .read_resources   = pci_dev_read_resources,
 406         .set_resources    = pci_dev_set_resources,
 407         .enable_resources = pci_dev_enable_resources,
 408         .init = 0,
 409         .scan_bus = 0,
 410 };
 411 struct device_operations default_pci_ops_bus = {
 412         .read_resources   = pci_bus_read_resources,
 413         .set_resources    = pci_dev_set_resources,
 414         .enable_resources = pci_bus_enable_resources,
 415         .init = 0,
 416         .scan_bus = pci_scan_bridge,
 417 };
 418 static void set_pci_ops(struct device *dev)
 419 {
 420         struct pci_driver *driver;
 421         if (dev->ops) {
 422                 return;
 423         }
 424         /* Look through the list of setup drivers and find one for
 425          * this pci device
 426          */
 427         for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
 428                 if ((driver->vendor == dev->vendor) &&
 429                         (driver->device == dev->device)) {
 430                         dev->ops = driver->ops;
 431 #if 1
 432                         printk_debug("%s [%04x/%04x] %sops\n",
 433                                 dev_path(dev),
 434                                 driver->vendor, driver->device,
 435                                 (driver->ops->scan_bus?"bus ":"")
 436                                 );
 437 #endif
 438                         return;
 439                 }
 440         }
 441         /* If I don't have a specific driver use the default operations */
 442         switch(dev->hdr_type & 0x7f) {  /* header type */
 443         case PCI_HEADER_TYPE_NORMAL:    /* standard header */
 444                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 445                         goto bad;
 446                 dev->ops = &default_pci_ops_dev;
 447                 break;
 448         case PCI_HEADER_TYPE_BRIDGE:
 449                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 450                         goto bad;
 451                 dev->ops = &default_pci_ops_bus;
 452                 break;
 453         default:
 454         bad:
 455                 printk_err("%s [%04x/%04x/%06x] has unknown header "
 456                         "type %02x, ignoring.\n",
 457                         dev_path(dev),
 458                         dev->vendor, dev->device,
 459                         dev->class >> 8, dev->hdr_type);
 460         }
 461         return;
 462 }
 463
 464 /**
 465  * Given a bus and a devfn number, find the device structure
 466  * @param bus The bus structure
 467  * @param devfn a device/function number
 468  * @return pointer to the device structure
 469  */
 470 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
 471 {
 472         struct device *dev = 0;
 473         for(; *list; list = &(*list)->sibling) {
 474                 if ((*list)->path.u.pci.devfn == devfn) {
 475                         /* Unlink from the list */
 476                         dev = *list;
 477                         *list = (*list)->sibling;
 478                         dev->sibling = 0;
 479                         break;
 480                 }
 481         }
 482         if (dev) {
 483                 device_t child;
 484                 /* Find the last child of our parent */
 485                 for(child = dev->bus->children; child && child->sibling; ) {
 486                         child = child->sibling;
 487                 }
 488                 /* Place the device on the list of children of it's parent. */
 489                 if (child) {
 490                         child->sibling = dev;
 491                 } else {
 492                         dev->bus->children = dev;
 493                 }
 494         }
 495
 496         return dev;
 497 }
 498
 499 void assign_id_set_links(device_t dev, uint8_t *pos,
 500                 uint8_t *previous_pos, unsigned previous_unitid,
 501                 unsigned last_unitid, int *reset_needed,
 502                 struct device *bus, unsigned *next_unitid)
 503 {
 504         static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
 505         static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
 506         uint16_t flags;
 507         struct bus prev_bus;
 508         struct device last, previous;
 509         unsigned count;
 510         uint8_t present_width_cap;
 511         uint16_t present_freq_cap;
 512         uint8_t upstream_width_cap;
 513         uint16_t upstream_freq_cap;
 514         uint8_t ln_upstream_width_in, ln_present_width_in;
 515         uint8_t ln_upstream_width_out, ln_present_width_out;
 516         uint16_t mask;
 517         uint8_t freq;
 518         uint8_t old_freq;
 519         uint8_t upstream_width, present_width;
 520         uint8_t old_width;
 521
 522         flags = pci_read_config16(dev, (*pos) + PCI_CAP_FLAGS);
 523         printk_debug("flags: 0x%04x\n", (unsigned)flags);
 524         if ((flags >> 13) != 0)
 525                 return; /* Entry is a Host */
 526         /* Entry is a Slave secondary */
 527         flags &= ~0x1f; /* mask out base unit ID */
 528         flags |= *next_unitid & 0x1f; /* assign ID */
 529         count = (flags >> 5) & 0x1f; /* get unit count */
 530         printk_debug("unitid: 0x%02x, count: 0x%02x\n",
 531                 *next_unitid, count);
 532         pci_write_config16(dev, (*pos) + PCI_CAP_FLAGS, flags);
 533         *next_unitid += count;
 534         if (previous_unitid == 0) { /* the link is back to the host */
 535                 prev_bus.secondary = 0;
 536                 /* calculate the previous pos for the host */
 537                 *previous_pos = 0x80;
 538                 previous.bus = &prev_bus;
 539                 previous.path.type        = DEVICE_PATH_PCI;
 540                 previous.path.u.pci.devfn = 0x18 << 3;
 541         #warning "FIXME we should not hard code this!"
 542         } else {
 543                 previous.bus              = bus;
 544                 previous.path.type        = DEVICE_PATH_PCI;
 545                 previous.path.u.pci.devfn = previous_unitid << 3;
 546         }
 547         last.bus              = bus;
 548         last.path.type        = DEVICE_PATH_PCI;
 549         last.path.u.pci.devfn = last_unitid << 3;
 550         /* Set link width and frequency */
 551         present_freq_cap = pci_read_config16(&last,
 552                         (*pos) + PCI_HT_CAP_SLAVE_FREQ_CAP0);
 553         present_width_cap = pci_read_config8(&last,
 554                         (*pos) + PCI_HT_CAP_SLAVE_WIDTH0);
 555         if(previous_unitid == 0) { /* the link is back to the host */
 556                 upstream_freq_cap = pci_read_config16(&previous,
 557                             (*previous_pos) + PCI_HT_CAP_HOST_FREQ_CAP);
 558                 upstream_width_cap = pci_read_config8(&previous,
 559                             (*previous_pos) + PCI_HT_CAP_HOST_WIDTH);
 560         }
 561         else { /* The link is back up the chain */
 562                 upstream_freq_cap = pci_read_config16(&previous,
 563                         (*previous_pos) + PCI_HT_CAP_SLAVE_FREQ_CAP1);
 564                 upstream_width_cap = pci_read_config8(&previous,
 565                         (*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1);
 566         }
 567         /* Calculate the highest possible frequency */
 568         /* Errata for 8131 - freq 5 has hardware problems don't support it */
 569         freq = log2(present_freq_cap & upstream_freq_cap & 0x1f);
 570
 571         /* Calculate the highest width */
 572         ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
 573         ln_present_width_out  = link_width_to_pow2[(present_width_cap >> 4) & 7];
 574         if (ln_upstream_width_in > ln_present_width_out) {
 575                 ln_upstream_width_in = ln_present_width_out;
 576         }
 577         upstream_width = pow2_to_link_width[ln_upstream_width_in];
 578         present_width  = pow2_to_link_width[ln_upstream_width_in] << 4;
 579
 580         ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
 581         ln_present_width_in   = link_width_to_pow2[present_width_cap & 7];
 582         if (ln_upstream_width_out > ln_present_width_in) {
 583                 ln_upstream_width_out = ln_present_width_in;
 584         }
 585         upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
 586         present_width  |= pow2_to_link_width[ln_upstream_width_out];
 587
 588         /* set the present device */
 589         old_freq = pci_read_config8(&last, (*pos) + PCI_HT_CAP_SLAVE_FREQ0);
 590         if(old_freq != freq) {
 591                 pci_write_config8(&last,
 592                                 (*pos) + PCI_HT_CAP_SLAVE_FREQ0, freq);
 593                 *reset_needed = 1;
 594                 printk_debug("HyperT FreqP old %x new %x\n",old_freq,freq);
 595         }
 596         old_width = pci_read_config8(&last,
 597                         (*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1);
 598         if(present_width != old_width) {
 599                 pci_write_config8(&last,
 600                         (*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1, present_width);
 601                 *reset_needed = 1;
 602                 printk_debug("HyperT widthP old %x new %x\n",
 603                                 old_width, present_width);
 604         }
 605         /* set the upstream device */
 606         if(previous_unitid == 0) { /* the link is back to the host */
 607                 old_freq = pci_read_config8(&previous,
 608                                 (*previous_pos) + PCI_HT_CAP_HOST_FREQ);
 609                 old_freq &= 0x0f;
 610                 if(freq != old_freq) {
 611                         pci_write_config8(&previous,
 612                             (*previous_pos) + PCI_HT_CAP_HOST_FREQ, freq);
 613                         *reset_needed = 1;
 614                         printk_debug("HyperT freqUH old %x new %x\n",
 615                                         old_freq, freq);
 616                 }
 617                 old_width = pci_read_config8(&previous,
 618                             (*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1);
 619                 if(upstream_width != old_width) {
 620                         pci_write_config8(&previous,
 621                         (*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1,
 622                                         upstream_width);
 623                         *reset_needed = 1;
 624                         printk_debug("HyperT widthUH old %x new %x\n",
 625                                         old_width, upstream_width);
 626                 }
 627         }
 628         else { /* The link is back up the chain */
 629                 old_freq = pci_read_config8(&previous,
 630                         (*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1);
 631                 old_freq &= 0x0f;
 632                 if(freq != old_freq) {
 633                         pci_write_config8(&previous,
 634                             (*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1,
 635                                 freq);
 636                         *reset_needed = 1;
 637                         printk_debug("HyperT freqUL old %x new %x\n",
 638                                         old_freq, freq);
 639                 }
 640                 old_width = pci_read_config8(&previous,
 641                         (*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1 + 1);
 642                 if(upstream_width != old_width) {
 643                         pci_write_config8(&previous,
 644                             (*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1,
 645                                         upstream_width);
 646                         *reset_needed = 1;
 647                         printk_debug("HyperT widthUL old %x new %x\n",
 648                                         old_width, upstream_width);
 649                 }
 650         }
 651         *previous_pos = *pos;
 652         *pos=0;
 653 }
 654
 655 #define HYPERTRANSPORT_SUPPORT 1
 656 /** Scan the pci bus devices and bridges.
 657  * @param bus pointer to the bus structure
 658  * @param min_devfn minimum devfn to look at in the scan usually 0x00
 659  * @param max_devfn maximum devfn to look at in the scan usually 0xff
 660  * @param max current bus number
 661  * @return The maximum bus number found, after scanning all subordinate busses
 662  */
 663 unsigned int pci_scan_bus(struct bus *bus,
 664         unsigned min_devfn, unsigned max_devfn,
 665         unsigned int max)
 666 {
 667         unsigned int devfn;
 668         device_t dev;
 669         device_t old_devices;
 670         device_t child;
 671 #if HYPERTRANSPORT_SUPPORT
 672         unsigned next_unitid, last_unitid, previous_unitid;
 673         int reset_needed = 0;
 674         uint8_t previous_pos;
 675 #endif
 676
 677         printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
 678
 679         old_devices = bus->children;
 680         bus->children = 0;
 681
 682         post_code(0x24);
 683
 684
 685 #if HYPERTRANSPORT_SUPPORT
 686         /* Spin through the devices and collapse any early
 687          * hypertransport enumeration.
 688          */
 689         for(devfn = min_devfn; devfn <= max_devfn; devfn += 8) {
 690                 struct device dummy;
 691                 uint32_t id;
 692                 uint8_t hdr_type, pos;
 693                 dummy.bus              = bus;
 694                 dummy.path.type        = DEVICE_PATH_PCI;
 695                 dummy.path.u.pci.devfn = devfn;
 696                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 697                 if (    (id == 0xffffffff) || (id == 0x00000000) ||
 698                         (id == 0x0000ffff) || (id == 0xffff0000)) {
 699                         continue;
 700                 }
 701                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 702                 pos = 0;
 703                 switch(hdr_type & 0x7f) {
 704                 case PCI_HEADER_TYPE_NORMAL:
 705                 case PCI_HEADER_TYPE_BRIDGE:
 706                         pos = PCI_CAPABILITY_LIST;
 707                         break;
 708                 }
 709                 if (pos > PCI_CAP_LIST_NEXT) {
 710                         pos = pci_read_config8(&dummy, pos);
 711                 }
 712                 while(pos != 0) {
 713                         uint8_t cap;
 714                         cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
 715                         printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
 716                         if (cap == PCI_CAP_ID_HT) {
 717                                 uint16_t flags;
 718                                 flags = pci_read_config16(&dummy,
 719                                                 pos + PCI_CAP_FLAGS);
 720                                 printk_debug("flags: 0x%04x\n",
 721                                                 (unsigned)flags);
 722                                 if ((flags >> 13) == 0) {
 723                                         /* Clear the unitid */
 724                                         flags &= ~0x1f;
 725                                         pci_write_config16(&dummy,
 726                                                 pos + PCI_CAP_FLAGS, flags);
 727                                         break;
 728                                 }
 729                         }
 730                         pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
 731                 }
 732         }
 733         /* If present assign unitid to a hypertransport chain */
 734         last_unitid = 0;
 735         next_unitid = 1;
 736         previous_pos = 0;
 737         do {
 738                 struct device dummy;
 739                 uint32_t id;
 740                 uint8_t hdr_type, pos;
 741
 742                 previous_unitid = last_unitid;
 743                 last_unitid = next_unitid;
 744
 745                 /* Read the next unassigned device off the stack */
 746                 dummy.bus              = bus;
 747                 dummy.path.type        = DEVICE_PATH_PCI;
 748                 dummy.path.u.pci.devfn = 0;
 749                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 750                 /* If the chain is enumerated quit */
 751                 if (id == 0xffffffff || id == 0x00000000 ||
 752                         id == 0x0000ffff || id == 0xffff0000) {
 753                         break;
 754                 }
 755                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 756                 pos = 0;
 757                 switch(hdr_type & 0x7f) {
 758                 case PCI_HEADER_TYPE_NORMAL:
 759                 case PCI_HEADER_TYPE_BRIDGE:
 760                         pos = PCI_CAPABILITY_LIST;
 761                         break;
 762                 }
 763                 if (pos > PCI_CAP_LIST_NEXT) {
 764                         pos = pci_read_config8(&dummy, pos);
 765                 }
 766                 while(pos != 0) {   /* loop through the linked list */
 767                         uint8_t cap;
 768                         cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
 769                         printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
 770                         if (cap == PCI_CAP_ID_HT) {
 771                                 assign_id_set_links(&dummy,&pos,&previous_pos,
 772                                                 previous_unitid, last_unitid,
 773                                                 &reset_needed, bus,
 774                                                 &next_unitid);
 775                         }
 776                         if(pos)
 777                                 pos = pci_read_config8(&dummy,
 778                                                 pos + PCI_CAP_LIST_NEXT);
 779                 }
 780         } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
 781 #if HAVE_HARD_RESET == 1
 782         if(reset_needed) {
 783                 printk_debug("HyperT reset needed\n");
 784                 boot_successful();
 785                 hard_reset();
 786         }
 787         printk_debug("HyperT reset not needed\n");
 788 #endif /* HAVE_HARD_RESET */
 789 #endif /* HYPERTRANSPORT_SUPPORT */
 790
 791         /* probe all devices on this bus with some optimization for non-existance and
 792            single funcion devices */
 793         for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
 794                 uint32_t id, class;
 795                 uint8_t hdr_type;
 796
 797                 /* First thing setup the device structure */
 798                 dev = pci_scan_get_dev(&old_devices, devfn);
 799
 800                 /* Detect if a device is present */
 801                 if (!dev) {
 802                         struct device dummy;
 803                         dummy.bus              = bus;
 804                         dummy.path.type        = DEVICE_PATH_PCI;
 805                         dummy.path.u.pci.devfn = devfn;
 806                         id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 807                         /* some broken boards return 0 if a slot is empty: */
 808                         if (    (id == 0xffffffff) || (id == 0x00000000) ||
 809                                 (id == 0x0000ffff) || (id == 0xffff0000))
 810                         {
 811                                 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
 812                                 if (PCI_FUNC(devfn) == 0x00) {
 813                                         /* if this is a function 0 device and it is not present,
 814                                            skip to next device */
 815                                         devfn += 0x07;
 816                                 }
 817                                 /* multi function device, skip to next function */
 818                                 continue;
 819                         }
 820                         dev = alloc_dev(bus, &dummy.path);
 821                 }
 822                 else {
 823                         /* Run the magic enable/disable sequence for the device */
 824                         if (dev->ops && dev->ops->enable) {
 825                                 dev->ops->enable(dev);
 826                         }
 827                         /* Now read the vendor and device id */
 828                         id = pci_read_config32(dev, PCI_VENDOR_ID);
 829                 }
 830
 831                 /* Read the rest of the pci configuration information */
 832                 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
 833                 class = pci_read_config32(dev, PCI_CLASS_REVISION);
 834
 835                 /* Store the interesting information in the device structure */
 836                 dev->vendor = id & 0xffff;
 837                 dev->device = (id >> 16) & 0xffff;
 838                 dev->hdr_type = hdr_type;
 839                 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
 840                 dev->class = class >> 8;
 841
 842                 /* Look at the vendor and device id, or at least the
 843                  * header type and class and figure out which set of configuration
 844                  * methods to use.
 845                  */
 846                 if (!dev->ops) {
 847                         set_pci_ops(dev);
 848                         /* Error if we don't have some pci operations for it */
 849                         if (!dev->ops) {
 850                                 printk_err("%s No device operations\n",
 851                                         dev_path(dev));
 852                                 continue;
 853                         }
 854                         /* Now run the magic enable/disable sequence for the device */
 855                         if (dev->ops && dev->ops->enable) {
 856                                 dev->ops->enable(dev);
 857                         }
 858                 }
 859
 860                 printk_debug("%s [%04x/%04x] %s\n",
 861                         dev_path(dev),
 862                         dev->vendor, dev->device,
 863                         dev->enable?"enabled": "disabled");
 864
 865                 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
 866                         /* if this is not a multi function device, don't waste time probe
 867                            another function. Skip to next device. */
 868                         devfn += 0x07;
 869                 }
 870         }
 871         post_code(0x25);
 872
 873         for(child = bus->children; child; child = child->sibling) {
 874                 if (!child->ops->scan_bus) {
 875                         continue;
 876                 }
 877                 max = child->ops->scan_bus(child, max);
 878         }
 879         /*
 880          * We've scanned the bus and so we know all about what's on
 881          * the other side of any bridges that may be on this bus plus
 882          * any devices.
 883          *
 884          * Return how far we've got finding sub-buses.
 885          */
 886         printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
 887         post_code(0x55);
 888         return max;
 889 }
 890
 891 /** Scan the bus, first for bridges and next for devices.
 892  * @param pci_bus pointer to the bus structure
 893  * @return The maximum bus number found, after scanning all subordinate busses
 894  */
 895 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
 896 {
 897         struct bus *bus;
 898         uint32_t buses;
 899         uint16_t cr;
 900
 901         bus = &dev->link[0];
 902         dev->links = 1;
 903
 904         /* Set up the primary, secondary and subordinate bus numbers. We have
 905          * no idea how many buses are behind this bridge yet, so we set the
 906          * subordinate bus number to 0xff for the moment
 907          */
 908         bus->secondary = ++max;
 909         bus->subordinate = 0xff;
 910
 911         /* Clear all status bits and turn off memory, I/O and master enables. */
 912         cr = pci_read_config16(dev, PCI_COMMAND);
 913         pci_write_config16(dev, PCI_COMMAND, 0x0000);
 914         pci_write_config16(dev, PCI_STATUS, 0xffff);
 915
 916         /*
 917          * Read the existing primary/secondary/subordinate bus
 918          * number configuration.
 919          */
 920         buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
 921
 922         /* Configure the bus numbers for this bridge: the configuration
 923          * transactions will not be propagated by the bridge if it is not
 924          * correctly configured
 925          */
 926         buses &= 0xff000000;
 927         buses |= (((unsigned int) (dev->bus->secondary) << 0) |
 928                 ((unsigned int) (bus->secondary) << 8) |
 929                 ((unsigned int) (bus->subordinate) << 16));
 930         pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 931
 932         /* Now we can scan all subordinate buses i.e. the bus hehind the bridge */
 933         max = pci_scan_bus(bus, 0x00, 0xff, max);
 934
 935         /* We know the number of buses behind this bridge. Set the subordinate
 936          *  bus number to its real value
 937          */
 938         bus->subordinate = max;
 939         buses = (buses & 0xff00ffff) |
 940                 ((unsigned int) (bus->subordinate) << 16);
 941         pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
 942         pci_write_config16(dev, PCI_COMMAND, cr);
 943
 944         return max;
 945 }