2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <part/hard_reset.h>
22 #include <part/fallback_boot.h>
25 static uint8_t pci_moving_config8(struct device *dev, unsigned reg)
27 uint8_t value, ones, zeroes;
28 value = pci_read_config8(dev, reg);
30 pci_write_config8(dev, reg, 0xff);
31 ones = pci_read_config8(dev, reg);
33 pci_write_config8(dev, reg, 0x00);
34 zeroes = pci_read_config8(dev, reg);
36 pci_write_config8(dev, reg, value);
41 static uint16_t pci_moving_config16(struct device *dev, unsigned reg)
43 uint16_t value, ones, zeroes;
44 value = pci_read_config16(dev, reg);
46 pci_write_config16(dev, reg, 0xffff);
47 ones = pci_read_config16(dev, reg);
49 pci_write_config16(dev, reg, 0x0000);
50 zeroes = pci_read_config16(dev, reg);
52 pci_write_config16(dev, reg, value);
57 static uint32_t pci_moving_config32(struct device *dev, unsigned reg)
59 uint32_t value, ones, zeroes;
60 value = pci_read_config32(dev, reg);
62 pci_write_config32(dev, reg, 0xffffffff);
63 ones = pci_read_config32(dev, reg);
65 pci_write_config32(dev, reg, 0x00000000);
66 zeroes = pci_read_config32(dev, reg);
68 pci_write_config32(dev, reg, value);
73 unsigned pci_find_capability(device_t dev, unsigned cap)
77 switch(dev->hdr_type & 0x7f) {
78 case PCI_HEADER_TYPE_NORMAL:
79 case PCI_HEADER_TYPE_BRIDGE:
80 pos = PCI_CAPABILITY_LIST;
83 if (pos > PCI_CAP_LIST_NEXT) {
84 pos = pci_read_config8(dev, pos);
86 while (pos != 0) { /* loop through the linked list */
88 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
89 if (this_cap == cap) {
96 /** Given a device and register, read the size of the BAR for that register.
97 * @param dev Pointer to the device structure
98 * @param resource Pointer to the resource structure
99 * @param index Address of the pci configuration register
101 struct resource *pci_get_resource(struct device *dev, unsigned long index)
103 struct resource *resource;
104 unsigned long value, attr;
105 resource_t moving, limit;
107 /* Initialize the resources to nothing */
108 resource = new_resource(dev, index);
110 /* Get the initial value */
111 value = pci_read_config32(dev, index);
113 /* See which bits move */
114 moving = pci_moving_config32(dev, index);
116 /* Initialize attr to the bits that do not move */
117 attr = value & ~moving;
119 /* If it is a 64bit resource look at the high half as well */
120 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
121 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
123 /* Find the high bits that move */
124 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
126 /* Find the resource constraints.
128 * Start by finding the bits that move. From there:
129 * - Size is the least significant bit of the bits that move.
130 * - Limit is all of the bits that move plus all of the lower bits.
131 * See PCI Spec 6.2.5.1 ...
136 resource->align = resource->gran = 0;
137 while (!(moving & resource->size)) {
138 resource->size <<= 1;
139 resource->align += 1;
142 resource->limit = limit = moving | (resource->size - 1);
145 * some broken hardware has read-only registers that do not
146 * really size correctly.
147 * Example: the acer m7229 has BARs 1-4 normally read-only.
148 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
149 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
150 * violation of the spec.
151 * We catch this case and ignore it by observing which bits move,
152 * This also catches the common case unimplemented registers
153 * that always read back as 0.
157 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
158 dev_path(dev), index, value);
161 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
162 /* An I/O mapped base address */
163 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
164 resource->flags |= IORESOURCE_IO;
165 /* I don't want to deal with 32bit I/O resources */
166 resource->limit = 0xffff;
168 /* A Memory mapped base address */
169 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
170 resource->flags |= IORESOURCE_MEM;
171 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
172 resource->flags |= IORESOURCE_PREFETCH;
174 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
175 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
177 resource->limit = 0xffffffffUL;
178 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
180 resource->limit = 0x000fffffUL;
181 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
183 resource->limit = 0xffffffffffffffffULL;
184 resource->flags |= IORESOURCE_PCI64;
190 /* Don't let the limit exceed which bits can move */
191 if (resource->limit > limit) {
192 resource->limit = limit;
195 if (resource->flags) {
196 printk_debug("%s %02x ->",
197 dev_path(dev), resource->index);
198 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
199 value, zeroes, ones, attr);
201 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s%s\n ",
204 resource->size, resource->limit,
205 (resource->flags == 0) ? "unused":
206 (resource->flags & IORESOURCE_IO)? "io":
207 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem",
208 (resource->flags & IORESOURCE_PCI64)?"64":"");
215 static void pci_get_rom_resource(struct device *dev, unsigned long index)
217 struct resource *resource;
219 resource_t moving, limit;
221 if ((dev->on_mainboard) && (dev->rom_address == 0)) {
222 //skip it if rom_address is not set in MB Config.lb
226 /* Initialize the resources to nothing */
227 resource = new_resource(dev, index);
229 /* Get the initial value */
230 value = pci_read_config32(dev, index);
232 /* See which bits move */
233 moving = pci_moving_config32(dev, index);
234 /* clear the Enable bit */
235 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
237 /* Find the resource constraints.
239 * Start by finding the bits that move. From there:
240 * - Size is the least significant bit of the bits that move.
241 * - Limit is all of the bits that move plus all of the lower bits.
242 * See PCI Spec 6.2.5.1 ...
248 resource->align = resource->gran = 0;
249 while (!(moving & resource->size)) {
250 resource->size <<= 1;
251 resource->align += 1;
254 resource->limit = limit = moving | (resource->size - 1);
259 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
260 dev_path(dev), index, value);
264 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
267 /* for on board device with embedded ROM image, the ROM image is at
268 * fixed address specified in the Config.lb, the dev->rom_address is
269 * inited by driver_pci_onboard_ops::enable_dev() */
270 if ((dev->on_mainboard) && (dev->rom_address != 0)) {
271 resource->base = dev->rom_address;
272 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
273 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
277 /** Read the base address registers for a given device.
278 * @param dev Pointer to the dev structure
279 * @param howmany How many registers to read (6 for device, 2 for bridge)
281 static void pci_read_bases(struct device *dev, unsigned int howmany, unsigned long rom)
285 for (index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
286 struct resource *resource;
287 resource = pci_get_resource(dev, index);
288 index += (resource->flags & IORESOURCE_PCI64)?8:4;
291 pci_get_rom_resource(dev, rom);
293 compact_resources(dev);
296 static void pci_set_resource(struct device *dev, struct resource *resource);
298 static void pci_record_bridge_resource( struct device *dev, resource_t moving,
299 unsigned index, unsigned long mask,
302 /* Initiliaze the constraints on the current bus */
303 struct resource *resource;
308 resource = new_resource(dev, index);
312 while((moving & step) == 0) {
316 resource->gran = gran;
317 resource->align = gran;
318 resource->limit = moving | (step - 1);
319 resource->flags = type | IORESOURCE_PCI_BRIDGE;
320 compute_allocate_resource(&dev->link[0], resource, mask, type);
321 /* If there is nothing behind the resource,
322 * clear it and forget it.
324 if (resource->size == 0) {
325 resource->base = moving;
326 resource->flags |= IORESOURCE_ASSIGNED;
327 resource->flags &= ~IORESOURCE_STORED;
328 pci_set_resource(dev, resource);
335 static void pci_bridge_read_bases(struct device *dev)
337 resource_t moving_base, moving_limit, moving;
339 /* See if the bridge I/O resources are implemented */
340 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
341 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
343 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
344 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
346 moving = moving_base & moving_limit;
348 /* Initialize the io space constraints on the current bus */
349 pci_record_bridge_resource(dev, moving, PCI_IO_BASE,
350 IORESOURCE_IO, IORESOURCE_IO);
352 /* See if the bridge prefmem resources are implemented */
353 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
354 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
356 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
357 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
359 moving = moving_base & moving_limit;
360 /* Initiliaze the prefetchable memory constraints on the current bus */
361 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
362 IORESOURCE_MEM | IORESOURCE_PREFETCH,
363 IORESOURCE_MEM | IORESOURCE_PREFETCH);
365 /* See if the bridge mem resources are implemented */
366 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
367 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
369 moving = moving_base & moving_limit;
371 /* Initialize the memory resources on the current bus */
372 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
373 IORESOURCE_MEM | IORESOURCE_PREFETCH,
376 compact_resources(dev);
379 void pci_dev_read_resources(struct device *dev)
383 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
386 void pci_bus_read_resources(struct device *dev)
390 pci_bridge_read_bases(dev);
391 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
394 static void pci_set_resource(struct device *dev, struct resource *resource)
396 resource_t base, end;
398 /* Make certain the resource has actually been set */
399 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
400 printk_err("ERROR: %s %02x not allocated\n",
401 dev_path(dev), resource->index);
405 /* If I have already stored this resource don't worry about it */
406 if (resource->flags & IORESOURCE_STORED) {
410 /* If the resources is substractive don't worry about it */
411 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
415 /* Only handle PCI memory and IO resources for now */
416 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
419 /* Enable the resources in the command register */
420 if (resource->size) {
421 if (resource->flags & IORESOURCE_MEM) {
422 dev->command |= PCI_COMMAND_MEMORY;
424 if (resource->flags & IORESOURCE_IO) {
425 dev->command |= PCI_COMMAND_IO;
427 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
428 dev->command |= PCI_COMMAND_MASTER;
431 /* Get the base address */
432 base = resource->base;
435 end = resource_end(resource);
437 /* Now store the resource */
438 resource->flags |= IORESOURCE_STORED;
439 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
440 unsigned long base_lo, base_hi;
442 * some chipsets allow us to set/clear the IO bit.
443 * (e.g. VIA 82c686a.) So set it to be safe)
445 base_lo = base & 0xffffffff;
446 base_hi = (base >> 32) & 0xffffffff;
447 if (resource->flags & IORESOURCE_IO) {
448 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
450 pci_write_config32(dev, resource->index, base_lo);
451 if (resource->flags & IORESOURCE_PCI64) {
452 pci_write_config32(dev, resource->index + 4, base_hi);
455 else if (resource->index == PCI_IO_BASE) {
456 /* set the IO ranges */
457 compute_allocate_resource(&dev->link[0], resource,
458 IORESOURCE_IO, IORESOURCE_IO);
459 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
460 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
461 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
462 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
464 else if (resource->index == PCI_MEMORY_BASE) {
465 /* set the memory range */
466 compute_allocate_resource(&dev->link[0], resource,
467 IORESOURCE_MEM | IORESOURCE_PREFETCH,
469 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
470 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
472 else if (resource->index == PCI_PREF_MEMORY_BASE) {
473 /* set the prefetchable memory range */
474 compute_allocate_resource(&dev->link[0], resource,
475 IORESOURCE_MEM | IORESOURCE_PREFETCH,
476 IORESOURCE_MEM | IORESOURCE_PREFETCH);
477 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
478 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
479 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
480 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
483 /* Don't let me think I stored the resource */
484 resource->flags &= ~IORESOURCE_STORED;
485 printk_err("ERROR: invalid resource->index %x\n",
488 report_resource_stored(dev, resource, "");
492 void pci_dev_set_resources(struct device *dev)
494 struct resource *resource, *last;
498 last = &dev->resource[dev->resources];
500 for (resource = &dev->resource[0]; resource < last; resource++) {
501 pci_set_resource(dev, resource);
503 for (link = 0; link < dev->links; link++) {
505 bus = &dev->link[link];
507 assign_resources(bus);
511 /* set a default latency timer */
512 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
514 /* set a default secondary latency timer */
515 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
516 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
519 /* zero the irq settings */
520 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
522 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
524 /* set the cache line size, so far 64 bytes is good for everyone */
525 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
528 void pci_dev_enable_resources(struct device *dev)
530 const struct pci_operations *ops;
533 /* Set the subsystem vendor and device id for mainboard devices */
535 if (dev->on_mainboard && ops && ops->set_subsystem) {
536 printk_debug("%s subsystem <- %02x/%02x\n",
538 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
539 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
540 ops->set_subsystem(dev,
541 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
542 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
544 command = pci_read_config16(dev, PCI_COMMAND);
545 command |= dev->command;
546 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
547 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
548 pci_write_config16(dev, PCI_COMMAND, command);
551 void pci_bus_enable_resources(struct device *dev)
555 #if CONFIG_CONSOLE_VGA == 1
556 /* enable IO in command register if there is VGA card
557 * connected with (even it does not claim IO resource) */
558 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
559 dev->command |= PCI_COMMAND_IO;
562 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
563 ctrl |= dev->link[0].bridge_ctrl;
564 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
565 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
566 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
568 pci_dev_enable_resources(dev);
570 enable_childrens_resources(dev);
573 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
575 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
576 ((device & 0xffff) << 16) | (vendor & 0xffff));
579 #if CONFIG_PCI_ROM_RUN == 1
580 void pci_dev_init(struct device *dev)
582 struct rom_header *rom, *ram;
584 rom = pci_rom_probe(dev);
587 ram = pci_rom_load(dev, rom);
595 /** Default device operation for PCI devices */
596 static struct pci_operations pci_dev_ops_pci = {
597 .set_subsystem = pci_dev_set_subsystem,
600 struct device_operations default_pci_ops_dev = {
601 .read_resources = pci_dev_read_resources,
602 .set_resources = pci_dev_set_resources,
603 .enable_resources = pci_dev_enable_resources,
604 #if CONFIG_PCI_ROM_RUN == 1
605 .init = pci_dev_init,
611 .ops_pci = &pci_dev_ops_pci,
614 /** Default device operations for PCI bridges */
615 static struct pci_operations pci_bus_ops_pci = {
619 struct device_operations default_pci_ops_bus = {
620 .read_resources = pci_bus_read_resources,
621 .set_resources = pci_dev_set_resources,
622 .enable_resources = pci_bus_enable_resources,
624 .scan_bus = pci_scan_bridge,
626 .ops_pci = &pci_bus_ops_pci,
630 * @brief Set up PCI device operation
637 static void set_pci_ops(struct device *dev)
639 struct pci_driver *driver;
644 /* Look through the list of setup drivers and find one for
647 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
648 if ((driver->vendor == dev->vendor) &&
649 (driver->device == dev->device))
651 dev->ops = driver->ops;
652 printk_debug("%s [%04x/%04x] %sops\n",
654 driver->vendor, driver->device,
655 (driver->ops->scan_bus?"bus ":""));
660 /* If I don't have a specific driver use the default operations */
661 switch(dev->hdr_type & 0x7f) { /* header type */
662 case PCI_HEADER_TYPE_NORMAL: /* standard header */
663 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
665 dev->ops = &default_pci_ops_dev;
667 case PCI_HEADER_TYPE_BRIDGE:
668 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
670 dev->ops = &default_pci_ops_bus;
675 printk_err("%s [%04x/%04x/%06x] has unknown header "
676 "type %02x, ignoring.\n",
678 dev->vendor, dev->device,
679 dev->class >> 8, dev->hdr_type);
686 * @brief See if we have already allocated a device structure for a given devfn.
688 * Given a linked list of PCI device structures and a devfn number, find the
689 * device structure correspond to the devfn, if present. This function also
690 * removes the device structure from the linked list.
692 * @param list the device structure list
693 * @param devfn a device/function number
695 * @return pointer to the device structure found or null of we have not
696 * allocated a device for this devfn yet.
698 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
702 for(; *list; list = &(*list)->sibling) {
703 if ((*list)->path.type != DEVICE_PATH_PCI) {
704 printk_err("child %s not a pci device\n",
708 if ((*list)->path.u.pci.devfn == devfn) {
709 /* Unlink from the list */
711 *list = (*list)->sibling;
716 /* Just like alloc_dev add the device to the list of device on the bus.
717 * When the list of devices was formed we removed all of the parents
718 * children, and now we are interleaving static and dynamic devices in
723 /* Find the last child of our parent */
724 for (child = dev->bus->children; child && child->sibling; ) {
725 child = child->sibling;
727 /* Place the device on the list of children of it's parent. */
729 child->sibling = dev;
731 dev->bus->children = dev;
739 * @brief Scan a PCI bus.
741 * Determine the existence of devices and bridges on a PCI bus. If there are
742 * bridges on the bus, recursively scan the buses behind the bridges.
744 * @param bus pointer to the bus structure
745 * @param min_devfn minimum devfn to look at in the scan usually 0x00
746 * @param max_devfn maximum devfn to look at in the scan usually 0xff
747 * @param max current bus number
749 * @return The maximum bus number found, after scanning all subordinate busses
751 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn,
756 device_t old_devices;
759 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
761 old_devices = bus->children;
766 /* probe all devices/functions on this bus with some optimization for
767 * non-existence and single funcion devices
769 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
773 /* First thing setup the device structure */
774 dev = pci_scan_get_dev(&old_devices, devfn);
776 /* Detect if a device is present */
780 dummy.path.type = DEVICE_PATH_PCI;
781 dummy.path.u.pci.devfn = devfn;
782 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
783 /* some broken boards return 0 if a slot is empty: */
784 if ((id == 0xffffffff) || (id == 0x00000000) ||
785 (id == 0x0000ffff) || (id == 0xffff0000))
787 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
788 if (PCI_FUNC(devfn) == 0x00) {
789 /* if this is a function 0 device and
791 * skip to next device
795 /* This function in a multi function device is
796 * not present, skip to the next function.
800 dev = alloc_dev(bus, &dummy.path);
803 /* Enable/disable the device. Once we have
804 * found the device specific operations this
805 * operations we will disable the device with
808 * This is geared toward devices that have subfunctions
809 * that do not show up by default.
811 * If a device is a stuff option on the motherboard
812 * it may be absent and enable_dev must cope.
815 if (dev->chip_ops && dev->chip_ops->enable_dev)
817 dev->chip_ops->enable_dev(dev);
819 /* Now read the vendor and device id */
820 id = pci_read_config32(dev, PCI_VENDOR_ID);
822 /* If the device does not have a pci id disable it.
823 * Possibly this is because we have already disabled
824 * the device. But this also handles optional devices
825 * that may not always show up.
827 if (id == 0xffffffff || id == 0x00000000 ||
828 id == 0x0000ffff || id == 0xffff0000)
831 printk_info("Disabling static device: %s\n",
837 /* Read the rest of the pci configuration information */
838 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
839 class = pci_read_config32(dev, PCI_CLASS_REVISION);
841 /* Store the interesting information in the device structure */
842 dev->vendor = id & 0xffff;
843 dev->device = (id >> 16) & 0xffff;
844 dev->hdr_type = hdr_type;
845 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
846 dev->class = class >> 8;
848 /* Architectural/System devices always need to
851 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
852 dev->command |= PCI_COMMAND_MASTER;
855 /* Look at the vendor and device id, or at least the
856 * header type and class and figure out which set of
857 * configuration methods to use. Unless we already
861 /* Error if we don't have some pci operations for it */
863 printk_err("%s No device operations\n",
868 /* Now run the magic enable/disable sequence for the device */
869 if (dev->ops && dev->ops->enable) {
870 dev->ops->enable(dev);
873 printk_debug("%s [%04x/%04x] %s\n",
875 dev->vendor, dev->device,
876 dev->enabled?"enabled": "disabled");
878 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
879 /* if this is not a multi function device,
880 * don't waste time probing another function.
881 * Skip to next device.
888 /* For all children that implement scan_bus (i.e. bridges)
889 * scan the bus behind that child.
891 for (child = bus->children; child; child = child->sibling) {
892 if (!child->enabled ||
894 !child->ops->scan_bus)
898 max = child->ops->scan_bus(child, max);
902 * We've scanned the bus and so we know all about what's on
903 * the other side of any bridges that may be on this bus plus
906 * Return how far we've got finding sub-buses.
908 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
914 * @brief Scan a PCI bridge and the buses behind the bridge.
916 * Determine the existence of buses behind the bridge. Set up the bridge
917 * according to the result of the scan.
919 * This function is the default scan_bus() method for PCI bridge devices.
921 * @param dev pointer to the bridge device
922 * @param max the highest bus number assgined up to now
924 * @return The maximum bus number found, after scanning all subordinate busses
926 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
932 printk_spew("%s for %s\n", __func__, dev_path(dev));
938 /* Set up the primary, secondary and subordinate bus numbers. We have
939 * no idea how many buses are behind this bridge yet, so we set the
940 * subordinate bus number to 0xff for the moment.
942 bus->secondary = ++max;
943 bus->subordinate = 0xff;
945 /* Clear all status bits and turn off memory, I/O and master enables. */
946 cr = pci_read_config16(dev, PCI_COMMAND);
947 pci_write_config16(dev, PCI_COMMAND, 0x0000);
948 pci_write_config16(dev, PCI_STATUS, 0xffff);
951 * Read the existing primary/secondary/subordinate bus
952 * number configuration.
954 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
956 /* Configure the bus numbers for this bridge: the configuration
957 * transactions will not be propagated by the bridge if it is not
958 * correctly configured.
961 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
962 ((unsigned int) (bus->secondary) << 8) |
963 ((unsigned int) (bus->subordinate) << 16));
964 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
966 /* Now we can scan all subordinate buses
967 * i.e. the bus behind the bridge.
969 max = pci_scan_bus(bus, 0x00, 0xff, max);
971 /* We know the number of buses behind this bridge. Set the subordinate
972 * bus number to its real value.
974 bus->subordinate = max;
975 buses = (buses & 0xff00ffff) |
976 ((unsigned int) (bus->subordinate) << 16);
977 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
978 pci_write_config16(dev, PCI_COMMAND, cr);
980 printk_spew("%s returns max %d\n", __func__, max);
985 Tell the EISA int controller this int must be level triggered
986 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
988 static void pci_level_irq(unsigned char intNum)
990 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
992 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
993 intBits |= (1 << intNum);
995 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
998 outb((unsigned char) intBits, 0x4d0);
999 outb((unsigned char) (intBits >> 8), 0x4d1);
1001 /* this seems like an error but is not ... */
1003 if (inb(0x4d0) != (intBits & 0xf)) {
1004 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1005 __func__, intBits &0xf, inb(0x4d0));
1007 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
1008 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1009 __func__, (intBits>>8) &0xf, inb(0x4d1));
1015 This function assigns IRQs for all functions contained within
1016 the indicated device address. If the device does not exist or does
1017 not require interrupts then this function has no effect.
1019 This function should be called for each PCI slot in your system.
1021 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1023 The particular irq #s that are passed in depend on the routing inside
1024 your southbridge and on your motherboard.
1028 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4])
1034 unsigned char readback;
1036 /* Each slot may contain up to eight functions */
1037 for (functNum = 0; functNum < 8; functNum++) {
1038 pdev = dev_find_slot(bus, (slot << 3) + functNum);
1041 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1043 // PCI spec says all other values are reserved
1044 if ((line >= 1) && (line <= 4)) {
1045 irq = pIntAtoD[line - 1];
1047 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1048 irq, bus, slot, functNum);
1050 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1051 pIntAtoD[line - 1]);
1053 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1054 printk_debug(" Readback = %d\n", readback);
1056 // Change to level triggered
1057 pci_level_irq(pIntAtoD[line - 1]);