2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <device/chip.h>
22 #include <part/hard_reset.h>
23 #include <part/fallback_boot.h>
25 /** Given a device and register, read the size of the BAR for that register.
26 * @param dev Pointer to the device structure
27 * @param resource Pointer to the resource structure
28 * @param index Address of the pci configuration register
30 static struct resource *pci_get_resource(struct device *dev, unsigned long index)
32 struct resource *resource;
33 uint32_t addr, size, base;
36 /* Initialize the resources to nothing */
37 resource = get_resource(dev, index);
39 addr = pci_read_config32(dev, index);
41 /* FIXME: more consideration for 64-bit PCI devices,
42 * we currently detect their size but otherwise
43 * treat them as 32-bit resources
46 pci_write_config32(dev, index, ~0);
47 size = pci_read_config32(dev, index);
49 /* get the minimum value the bar can be set to */
50 pci_write_config32(dev, index, 0);
51 base = pci_read_config32(dev, index);
54 pci_write_config32(dev, index, addr);
57 * some broken hardware has read-only registers that do not
58 * really size correctly. You can tell this if addr == size
59 * Example: the acer m7229 has BARs 1-4 normally read-only.
60 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
61 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
62 * violation of the spec.
63 * We catch this case and ignore it by settting size and type to 0.
64 * This incidentally catches the common case where registers
65 * read back as 0 for both address and size.
67 if ((addr == size) && (addr == base)) {
70 "%s register %02x(%08x), read-only ignoring it\n",
76 /* Now compute the actual size, See PCI Spec 6.2.5.1 ... */
77 else if (size & PCI_BASE_ADDRESS_SPACE_IO) {
78 type = size & (~PCI_BASE_ADDRESS_IO_MASK);
79 /* BUG! Top 16 bits can be zero (or not)
80 * So set them to 0xffff so they go away ...
82 resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1;
83 resource->align = log2(resource->size);
84 resource->gran = resource->align;
85 resource->flags |= IORESOURCE_IO;
86 resource->limit = 0xffff;
89 /* A Memory mapped base address */
90 type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
91 resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1;
92 resource->align = log2(resource->size);
93 resource->gran = resource->align;
94 resource->flags |= IORESOURCE_MEM;
95 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
96 resource->flags |= IORESOURCE_PREFETCH;
98 type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
99 if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) {
101 resource->limit = 0xffffffffUL;
103 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) {
105 resource->limit = 0x000fffffUL;
107 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
108 unsigned long index_hi;
110 * For now just treat this as a 32bit limit
112 index_hi = index + 4;
113 resource->limit = 0xffffffffUL;
114 resource->flags |= IORESOURCE_PCI64;
115 addr = pci_read_config32( dev, index_hi);
116 /* get the extended size */
117 pci_write_config32(dev, index_hi, 0xffffffffUL);
118 size = pci_read_config32( dev, index_hi);
120 /* get the minimum value the bar can be set to */
121 pci_write_config32(dev, index_hi, 0);
122 base = pci_read_config32(dev, index_hi);
125 pci_write_config32(dev, index_hi, addr);
127 if ((size == 0xffffffff) && (base == 0)) {
128 /* Clear the top half of the bar */
129 pci_write_config32(dev, index_hi, 0);
132 printk_err("%s Unable to handle 64-bit address\n",
134 resource->flags = IORESOURCE_PCI64;
142 /* dev->size holds the flags... */
146 /** Read the base address registers for a given device.
147 * @param dev Pointer to the dev structure
148 * @param howmany How many registers to read (6 for device, 2 for bridge)
150 static void pci_read_bases(struct device *dev, unsigned int howmany)
154 for (index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
155 struct resource *resource;
156 resource = pci_get_resource(dev, index);
157 index += (resource->flags & IORESOURCE_PCI64)?8:4;
159 compact_resources(dev);
162 static void pci_bridge_read_bases(struct device *dev)
164 struct resource *resource;
166 /* FIXME handle bridges without some of the optional resources */
168 /* Initialize the io space constraints on the current bus */
169 resource = get_resource(dev, PCI_IO_BASE);
171 resource->align = log2(PCI_IO_BRIDGE_ALIGN);
172 resource->gran = log2(PCI_IO_BRIDGE_ALIGN);
173 resource->limit = 0xffffUL;
174 resource->flags |= IORESOURCE_IO | IORESOURCE_PCI_BRIDGE;
175 compute_allocate_resource(&dev->link[0], resource,
176 IORESOURCE_IO, IORESOURCE_IO);
178 /* Initiliaze the prefetchable memory constraints on the current bus */
179 resource = get_resource(dev, PCI_PREF_MEMORY_BASE);
181 resource->align = log2(PCI_MEM_BRIDGE_ALIGN);
182 resource->gran = log2(PCI_MEM_BRIDGE_ALIGN);
183 resource->limit = 0xffffffffUL;
184 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE;
185 resource->index = PCI_PREF_MEMORY_BASE;
186 compute_allocate_resource(&dev->link[0], resource,
187 IORESOURCE_MEM | IORESOURCE_PREFETCH,
188 IORESOURCE_MEM | IORESOURCE_PREFETCH);
190 /* Initialize the memory resources on the current bus */
191 resource = get_resource(dev, PCI_MEMORY_BASE);
193 resource->align = log2(PCI_MEM_BRIDGE_ALIGN);
194 resource->gran = log2(PCI_MEM_BRIDGE_ALIGN);
195 resource->limit = 0xffffffffUL;
196 resource->flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE;
197 compute_allocate_resource(&dev->link[0], resource,
198 IORESOURCE_MEM | IORESOURCE_PREFETCH,
201 compact_resources(dev);
204 void pci_dev_read_resources(struct device *dev)
208 pci_read_bases(dev, 6);
210 addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
211 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
214 void pci_bus_read_resources(struct device *dev)
218 pci_bridge_read_bases(dev);
219 pci_read_bases(dev, 2);
221 addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
222 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
226 * @brief round a number up to an alignment.
227 * @param val the starting value
228 * @param roundup Alignment as a power of two
229 * @returns rounded up number
231 static unsigned long round(unsigned long val, unsigned long roundup)
233 /* ROUNDUP MUST BE A POWER OF TWO. */
234 unsigned long inverse;
235 inverse = ~(roundup - 1);
236 val += (roundup - 1);
241 static void pci_set_resource(struct device *dev, struct resource *resource)
243 unsigned long base, limit;
244 unsigned char buf[10];
247 /* Make certain the resource has actually been set */
249 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
250 printk_err("ERROR: %s %02x not allocated\n",
251 dev_path(dev), resource->index);
255 /* If I have already stored this resource don't worry about it */
256 if (resource->flags & IORESOURCE_STORED) {
260 /* Only handle PCI memory and IO resources for now */
261 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
264 if (resource->flags & IORESOURCE_MEM) {
265 dev->command |= PCI_COMMAND_MEMORY;
267 if (resource->flags & IORESOURCE_IO) {
268 dev->command |= PCI_COMMAND_IO;
270 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
271 dev->command |= PCI_COMMAND_MASTER;
274 /* Get the base address */
275 base = resource->base;
277 /* Get the resource granularity */
278 gran = 1UL << resource->gran;
280 /* For a non bridge resource granularity and alignment are the same.
281 * For a bridge resource align is the largest needed alignment below
282 * the bridge. While the granularity is simply how many low bits of the
283 * address cannot be set.
286 /* Get the limit (rounded up) */
287 limit = base + round(resource->size, gran) - 1UL;
289 /* Now store the resource */
290 resource->flags |= IORESOURCE_STORED;
291 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
292 /* some chipsets allow us to set/clear the IO bit.
293 * (e.g. VIA 82c686a.) So set it to be safe) */
294 limit = base + resource->size -1;
295 if (resource->flags & IORESOURCE_IO) {
296 base |= PCI_BASE_ADDRESS_SPACE_IO;
298 pci_write_config32(dev, resource->index, base & 0xffffffff);
299 if (resource->flags & IORESOURCE_PCI64) {
300 /* FIXME handle real 64bit base addresses */
301 pci_write_config32(dev, resource->index + 4, 0);
303 } else if (resource->index == PCI_IO_BASE) {
305 * WARNING: we don't really do 32-bit addressing for IO yet!
307 compute_allocate_resource(&dev->link[0], resource,
308 IORESOURCE_IO, IORESOURCE_IO);
309 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
310 pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
311 pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0);
312 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0);
313 } else if (resource->index == PCI_MEMORY_BASE) {
314 /* set the memory range */
315 compute_allocate_resource(&dev->link[0], resource,
316 IORESOURCE_MEM | IORESOURCE_PREFETCH,
318 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
319 pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
320 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
321 /* set the prefetchable memory range
322 * WARNING: we don't really do 64-bit addressing for
323 * prefetchable memory yet! */
324 compute_allocate_resource(&dev->link[0], resource,
325 IORESOURCE_MEM | IORESOURCE_PREFETCH,
326 IORESOURCE_MEM | IORESOURCE_PREFETCH);
327 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
328 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
329 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0);
330 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0);
332 /* Don't let me think I stored the resource */
333 resource->flags &= ~IORESOURCE_STORED;
334 printk_err("ERROR: invalid resource->index %x\n",
339 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
340 sprintf(buf, "bus %d ", dev->link[0].secondary);
342 printk_debug("%s %02x <- [0x%08lx - 0x%08lx] %s%s\n",
343 dev_path(dev), resource->index, resource->base,
345 (resource->flags & IORESOURCE_IO)? "io":
346 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
350 void pci_dev_set_resources(struct device *dev)
352 struct resource *resource, *last;
356 last = &dev->resource[dev->resources];
357 for (resource = &dev->resource[0]; resource < last; resource++) {
358 pci_set_resource(dev, resource);
361 for (link = 0; link < dev->links; link++) {
363 bus = &dev->link[link];
365 assign_resources(bus);
369 /* set a default latency timer */
370 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
372 /* set a default secondary latency timer */
373 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
374 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
377 /* zero the irq settings */
378 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
380 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
382 /* set the cache line size, so far 64 bytes is good for everyone */
383 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
386 void pci_dev_enable_resources(struct device *dev)
389 command = pci_read_config16(dev, PCI_COMMAND);
390 command |= dev->command;
391 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
392 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
393 pci_write_config16(dev, PCI_COMMAND, command);
395 enable_childrens_resources(dev);
398 void pci_bus_enable_resources(struct device *dev)
401 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
402 ctrl |= dev->link[0].bridge_ctrl;
403 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
404 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
405 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
407 pci_dev_enable_resources(dev);
410 /** Default device operation for PCI devices */
411 struct device_operations default_pci_ops_dev = {
412 .read_resources = pci_dev_read_resources,
413 .set_resources = pci_dev_set_resources,
414 .enable_resources = pci_dev_enable_resources,
419 /** Default device operations for PCI bridges */
420 struct device_operations default_pci_ops_bus = {
421 .read_resources = pci_bus_read_resources,
422 .set_resources = pci_dev_set_resources,
423 .enable_resources = pci_bus_enable_resources,
425 .scan_bus = pci_scan_bridge,
429 * @brief Set up PCI device operation
436 static void set_pci_ops(struct device *dev)
438 struct pci_driver *driver;
444 /* Look through the list of setup drivers and find one for
446 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
447 if ((driver->vendor == dev->vendor) &&
448 (driver->device == dev->device)) {
449 dev->ops = driver->ops;
451 printk_debug("%s [%04x/%04x] %sops\n", dev_path(dev),
452 driver->vendor, driver->device,
453 (driver->ops->scan_bus?"bus ":""));
460 extern struct pci_driver generic_vga_driver;
461 /* TODO: Install generic VGA driver for VGA devices, base on the
463 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
464 printk_debug("setting up generic VGA driver\n");
465 dev->ops = generic_vga_driver.ops;
470 /* If I don't have a specific driver use the default operations */
471 switch(dev->hdr_type & 0x7f) { /* header type */
472 case PCI_HEADER_TYPE_NORMAL: /* standard header */
473 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
475 dev->ops = &default_pci_ops_dev;
477 case PCI_HEADER_TYPE_BRIDGE:
478 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
480 dev->ops = &default_pci_ops_bus;
485 printk_err("%s [%04x/%04x/%06x] has unknown header "
486 "type %02x, ignoring.\n",
488 dev->vendor, dev->device,
489 dev->class >> 8, dev->hdr_type);
496 * @brief Find a specific device structure on a list of device structures
498 * Given a linked list of PCI device structures and a devfn number, find the
499 * device structure correspond to the devfn.
501 * @param list the device structure list
502 * @param devfn a device/function number
504 * @return pointer to the device structure found
506 static struct device *pci_scan_get_dev(struct device **list,
509 struct device *dev = 0;
511 for (; *list; list = &(*list)->sibling) {
512 if ((*list)->path.type != DEVICE_PATH_PCI) {
513 printk_err("child %s not a pci device\n",
517 if ((*list)->path.u.pci.devfn == devfn) {
518 /* Unlink from the list */
520 *list = (*list)->sibling;
526 /* FIXME: why are we doing this ? Isn't there some order between the
527 * structures before ? */
530 /* Find the last child of our parent */
531 for (child = dev->bus->children; child && child->sibling; ) {
532 child = child->sibling;
534 /* Place the device on the list of children of it's parent. */
536 child->sibling = dev;
538 dev->bus->children = dev;
546 * @brief Scan a PCI bus
548 * Determine the existence of devices and bridges on a PCI bus. If there are
549 * bridges on the bus, recursively scan the buses behind the bridges.
551 * This function is the default scan_bus() method for the root device
554 * @param bus pointer to the bus structure
555 * @param min_devfn minimum devfn to look at in the scan usually 0x00
556 * @param max_devfn maximum devfn to look at in the scan usually 0xff
557 * @param max current bus number
559 * @return The maximum bus number found, after scanning all subordinate busses
561 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
562 unsigned max_devfn, unsigned int max)
566 device_t old_devices;
569 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
571 old_devices = bus->children;
576 /* probe all devices/functions on this bus with some optimization for
577 * non-existence and single funcion devices */
578 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
582 /* device structures for PCI devices associated with static
583 * devices are already created during the static device
584 * enumeration, find out if it is the case for this devfn */
585 dev = pci_scan_get_dev(&old_devices, devfn);
588 /* it's not associated with a static device, detect if
589 * this device is present */
592 dummy.path.type = DEVICE_PATH_PCI;
593 dummy.path.u.pci.devfn = devfn;
594 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
595 /* some broken boards return 0 if a slot is empty: */
596 if ((id == 0xffffffff) || (id == 0x00000000) ||
597 (id == 0x0000ffff) || (id == 0xffff0000)) {
598 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n",
600 if (PCI_FUNC(devfn) == 0x00) {
601 /* if this is a function 0 device and
602 * it is not present, skip to next
606 /* this function in a multi function device is
607 * not present, skip to next function */
610 dev = alloc_dev(bus, &dummy.path);
612 /* Run the magic enable/disable sequence for the
614 /* FIXME: What happen if this PCI device listed as
615 * static device but does not exist ? This calls
616 * some arbitray code without any justification
617 * Also, it calls the enable function regardlessly
618 * the value of dev->enabled */
619 if (dev->chip && dev->chip->control &&
620 dev->chip->control->enable_dev) {
621 int enabled = dev->enabled;
623 dev->chip->control->enable_dev(dev);
624 dev->enabled = enabled;
626 /* Now read the vendor and device id */
627 id = pci_read_config32(dev, PCI_VENDOR_ID);
629 /* Read the rest of the pci configuration information */
630 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
631 class = pci_read_config32(dev, PCI_CLASS_REVISION);
633 /* Store the interesting information in the device structure */
634 dev->vendor = id & 0xffff;
635 dev->device = (id >> 16) & 0xffff;
636 dev->hdr_type = hdr_type;
637 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
638 dev->class = class >> 8;
640 /* Look at the vendor and device id, or at least the
641 * header type and class and figure out which set of
642 * configuration methods to use. Unless we already
646 /* Error if we don't have some pci operations for it */
648 printk_err("%s No device operations\n",
653 /* Now run the magic enable/disable sequence for the device */
654 if (dev->ops && dev->ops->enable) {
655 dev->ops->enable(dev);
656 } else if (dev->chip && dev->chip->control &&
657 dev->chip->control->enable_dev) {
658 dev->chip->control->enable_dev(dev);
661 printk_debug("%s [%04x/%04x] %s\n",
663 dev->vendor, dev->device,
664 dev->enabled?"enabled": "disabled");
666 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
667 /* if this is not a multi function device, don't
668 * waste time probe another function.
669 * Skip to next device. */
675 /* if a child provides scan_bus(), for example a bridge, scan
676 * buses behind that child */
677 for (child = bus->children; child; child = child->sibling) {
678 if (!child->ops->scan_bus) {
681 max = child->ops->scan_bus(child, max);
685 * We've scanned the bus and so we know all about what's on
686 * the other side of any bridges that may be on this bus plus
689 * Return how far we've got finding sub-buses.
691 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
697 * @brief Scan a PCI bridge and the buses behind the bridge.
699 * Determine the existence of buses behind the bridge. Set up the bridge
700 * according to the result of the scan.
702 * This function is the default scan_bus() method for PCI bridge devices.
704 * @param dev pointer to the bridge device
705 * @param max the highest bus number assgined up to now
707 * @return The maximum bus number found, after scanning all subordinate busses
709 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
718 /* Set up the primary, secondary and subordinate bus numbers. We have
719 * no idea how many buses are behind this bridge yet, so we set the
720 * subordinate bus number to 0xff for the moment. */
721 bus->secondary = ++max;
722 bus->subordinate = 0xff;
724 /* Clear all status bits and turn off memory, I/O and master enables. */
725 cr = pci_read_config16(dev, PCI_COMMAND);
726 pci_write_config16(dev, PCI_COMMAND, 0x0000);
727 pci_write_config16(dev, PCI_STATUS, 0xffff);
729 /* Read the existing primary/secondary/subordinate bus
730 * number configuration. */
731 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
733 /* Configure the bus numbers for this bridge: the configuration
734 * transactions will not be propagated by the bridge if it is not
735 * correctly configured */
737 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
738 ((unsigned int) (bus->secondary) << 8) |
739 ((unsigned int) (bus->subordinate) << 16));
740 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
742 /* Now we can scan all subordinate buses i.e. the buses behind the
744 max = pci_scan_bus(bus, 0x00, 0xff, max);
746 /* We know the number of buses behind this bridge. Set the subordinate
747 * bus number to its real value */
748 bus->subordinate = max;
749 buses = (buses & 0xff00ffff) |
750 ((unsigned int) (bus->subordinate) << 16);
751 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
752 pci_write_config16(dev, PCI_COMMAND, cr);
754 printk_spew("%s returns max %d\n", __FUNCTION__, max);
759 Tell the EISA int controller this int must be level triggered
760 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
762 static void pci_level_irq(unsigned char intNum)
764 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
766 printk_spew("%s: current ints are 0x%x\n", __FUNCTION__, intBits);
767 intBits |= (1 << intNum);
769 printk_spew("%s: try to set ints 0x%x\n", __FUNCTION__, intBits);
772 outb((unsigned char) intBits, 0x4d0);
773 outb((unsigned char) (intBits >> 8), 0x4d1);
775 /* this seems like an error but is not ... */
777 if (inb(0x4d0) != (intBits & 0xf)) {
778 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
779 __FUNCTION__, intBits &0xf, inb(0x4d0));
781 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
782 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
783 __FUNCTION__, (intBits>>8) &0xf, inb(0x4d1));
789 This function assigns IRQs for all functions contained within
790 the indicated device address. If the device does not exist or does
791 not require interrupts then this function has no effect.
793 This function should be called for each PCI slot in your system.
795 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
797 The particular irq #s that are passed in depend on the routing inside
798 your southbridge and on your motherboard.
802 void pci_assign_irqs(unsigned bus, unsigned slot,
803 const unsigned char pIntAtoD[4])
809 unsigned char readback;
811 /* Each slot may contain up to eight functions */
812 for (functNum = 0; functNum < 8; functNum++) {
813 pdev = dev_find_slot(bus, (slot << 3) + functNum);
816 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
818 // PCI spec says all other values are reserved
819 if ((line >= 1) && (line <= 4)) {
820 irq = pIntAtoD[line - 1];
822 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
823 irq, bus, slot, functNum);
825 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
828 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
829 printk_debug(" Readback = %d\n", readback);
831 // Change to level triggered
832 pci_level_irq(pIntAtoD[line - 1]);