2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <part/hard_reset.h>
22 #include <part/fallback_boot.h>
24 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
25 #include <device/hypertransport.h>
27 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
28 #include <device/pcix.h>
30 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
31 #include <device/pciexp.h>
33 #if CONFGI_AGP_PLUGIN_SUPPORT == 1
34 #include <device/agp.h>
36 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
37 #include <device/cardbus.h>
40 uint8_t pci_moving_config8(struct device *dev, unsigned reg)
42 uint8_t value, ones, zeroes;
43 value = pci_read_config8(dev, reg);
45 pci_write_config8(dev, reg, 0xff);
46 ones = pci_read_config8(dev, reg);
48 pci_write_config8(dev, reg, 0x00);
49 zeroes = pci_read_config8(dev, reg);
51 pci_write_config8(dev, reg, value);
56 uint16_t pci_moving_config16(struct device *dev, unsigned reg)
58 uint16_t value, ones, zeroes;
59 value = pci_read_config16(dev, reg);
61 pci_write_config16(dev, reg, 0xffff);
62 ones = pci_read_config16(dev, reg);
64 pci_write_config16(dev, reg, 0x0000);
65 zeroes = pci_read_config16(dev, reg);
67 pci_write_config16(dev, reg, value);
72 uint32_t pci_moving_config32(struct device *dev, unsigned reg)
74 uint32_t value, ones, zeroes;
75 value = pci_read_config32(dev, reg);
77 pci_write_config32(dev, reg, 0xffffffff);
78 ones = pci_read_config32(dev, reg);
80 pci_write_config32(dev, reg, 0x00000000);
81 zeroes = pci_read_config32(dev, reg);
83 pci_write_config32(dev, reg, value);
88 unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last)
94 status = pci_read_config16(dev, PCI_STATUS);
95 if (!(status & PCI_STATUS_CAP_LIST)) {
98 switch(dev->hdr_type & 0x7f) {
99 case PCI_HEADER_TYPE_NORMAL:
100 case PCI_HEADER_TYPE_BRIDGE:
101 pos = PCI_CAPABILITY_LIST;
103 case PCI_HEADER_TYPE_CARDBUS:
104 pos = PCI_CB_CAPABILITY_LIST;
109 pos = pci_read_config8(dev, pos);
110 while(reps-- && (pos >= 0x40)) { /* loop through the linked list */
113 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
114 printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
115 if (this_cap == 0xff) {
118 if (!last && (this_cap == cap)) {
124 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
129 unsigned pci_find_capability(device_t dev, unsigned cap)
131 return pci_find_next_capability(dev, cap, 0);
135 /** Given a device and register, read the size of the BAR for that register.
136 * @param dev Pointer to the device structure
137 * @param resource Pointer to the resource structure
138 * @param index Address of the pci configuration register
140 struct resource *pci_get_resource(struct device *dev, unsigned long index)
142 struct resource *resource;
143 unsigned long value, attr;
144 resource_t moving, limit;
146 /* Initialize the resources to nothing */
147 resource = new_resource(dev, index);
149 /* Get the initial value */
150 value = pci_read_config32(dev, index);
152 /* See which bits move */
153 moving = pci_moving_config32(dev, index);
155 /* Initialize attr to the bits that do not move */
156 attr = value & ~moving;
158 /* If it is a 64bit resource look at the high half as well */
159 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
160 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
162 /* Find the high bits that move */
163 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
165 /* Find the resource constraints.
167 * Start by finding the bits that move. From there:
168 * - Size is the least significant bit of the bits that move.
169 * - Limit is all of the bits that move plus all of the lower bits.
170 * See PCI Spec 6.2.5.1 ...
175 resource->align = resource->gran = 0;
176 while(!(moving & resource->size)) {
177 resource->size <<= 1;
178 resource->align += 1;
181 resource->limit = limit = moving | (resource->size - 1);
184 * some broken hardware has read-only registers that do not
185 * really size correctly.
186 * Example: the acer m7229 has BARs 1-4 normally read-only.
187 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
188 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
189 * violation of the spec.
190 * We catch this case and ignore it by observing which bits move,
191 * This also catches the common case unimplemented registers
192 * that always read back as 0.
197 "%s register %02x(%08x), read-only ignoring it\n",
198 dev_path(dev), index, value);
202 else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
203 /* An I/O mapped base address */
204 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
205 resource->flags |= IORESOURCE_IO;
206 /* I don't want to deal with 32bit I/O resources */
207 resource->limit = 0xffff;
210 /* A Memory mapped base address */
211 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
212 resource->flags |= IORESOURCE_MEM;
213 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
214 resource->flags |= IORESOURCE_PREFETCH;
216 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
217 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
219 resource->limit = 0xffffffffUL;
221 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
223 resource->limit = 0x000fffffUL;
225 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
227 resource->limit = 0xffffffffffffffffULL;
228 resource->flags |= IORESOURCE_PCI64;
235 /* Don't let the limit exceed which bits can move */
236 if (resource->limit > limit) {
237 resource->limit = limit;
240 if (resource->flags) {
241 printk_debug("%s %02x ->",
242 dev_path(dev), resource->index);
243 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
244 value, zeroes, ones, attr);
246 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ",
249 resource->size, resource->limit,
250 resource_type(resource));
257 static void pci_get_rom_resource(struct device *dev, unsigned long index)
259 struct resource *resource;
261 resource_t moving, limit;
263 if ((dev->on_mainboard) && (dev->rom_address == 0)) {
264 //skip it if rom_address is not set in MB Config.lb
268 /* Initialize the resources to nothing */
269 resource = new_resource(dev, index);
271 /* Get the initial value */
272 value = pci_read_config32(dev, index);
274 /* See which bits move */
275 moving = pci_moving_config32(dev, index);
276 /* clear the Enable bit */
277 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
279 /* Find the resource constraints.
281 * Start by finding the bits that move. From there:
282 * - Size is the least significant bit of the bits that move.
283 * - Limit is all of the bits that move plus all of the lower bits.
284 * See PCI Spec 6.2.5.1 ...
290 resource->align = resource->gran = 0;
291 while (!(moving & resource->size)) {
292 resource->size <<= 1;
293 resource->align += 1;
296 resource->limit = limit = moving | (resource->size - 1);
301 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
302 dev_path(dev), index, value);
306 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
309 /* for on board device with embedded ROM image, the ROM image is at
310 * fixed address specified in the Config.lb, the dev->rom_address is
311 * inited by driver_pci_onboard_ops::enable_dev() */
312 if ((dev->on_mainboard) && (dev->rom_address != 0)) {
313 resource->base = dev->rom_address;
314 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
315 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
318 compact_resources(dev);
321 /** Read the base address registers for a given device.
322 * @param dev Pointer to the dev structure
323 * @param howmany How many registers to read (6 for device, 2 for bridge)
325 static void pci_read_bases(struct device *dev, unsigned int howmany)
329 for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
330 struct resource *resource;
331 resource = pci_get_resource(dev, index);
332 index += (resource->flags & IORESOURCE_PCI64)?8:4;
335 compact_resources(dev);
338 static void pci_set_resource(struct device *dev, struct resource *resource);
340 static void pci_record_bridge_resource(
341 struct device *dev, resource_t moving,
342 unsigned index, unsigned long mask, unsigned long type)
344 /* Initiliaze the constraints on the current bus */
345 struct resource *resource;
350 resource = new_resource(dev, index);
354 while((moving & step) == 0) {
358 resource->gran = gran;
359 resource->align = gran;
360 resource->limit = moving | (step - 1);
361 resource->flags = type | IORESOURCE_PCI_BRIDGE;
362 compute_allocate_resource(&dev->link[0], resource, mask, type);
363 /* If there is nothing behind the resource,
364 * clear it and forget it.
366 if (resource->size == 0) {
367 resource->base = moving;
368 resource->flags |= IORESOURCE_ASSIGNED;
369 resource->flags &= ~IORESOURCE_STORED;
370 pci_set_resource(dev, resource);
377 static void pci_bridge_read_bases(struct device *dev)
379 resource_t moving_base, moving_limit, moving;
381 /* See if the bridge I/O resources are implemented */
382 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
383 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
385 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
386 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
388 moving = moving_base & moving_limit;
390 /* Initialize the io space constraints on the current bus */
391 pci_record_bridge_resource(
392 dev, moving, PCI_IO_BASE,
393 IORESOURCE_IO, IORESOURCE_IO);
396 /* See if the bridge prefmem resources are implemented */
397 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
398 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
400 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
401 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
403 moving = moving_base & moving_limit;
404 /* Initiliaze the prefetchable memory constraints on the current bus */
405 pci_record_bridge_resource(
406 dev, moving, PCI_PREF_MEMORY_BASE,
407 IORESOURCE_MEM | IORESOURCE_PREFETCH,
408 IORESOURCE_MEM | IORESOURCE_PREFETCH);
411 /* See if the bridge mem resources are implemented */
412 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
413 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
415 moving = moving_base & moving_limit;
417 /* Initialize the memory resources on the current bus */
418 pci_record_bridge_resource(
419 dev, moving, PCI_MEMORY_BASE,
420 IORESOURCE_MEM | IORESOURCE_PREFETCH,
423 compact_resources(dev);
426 void pci_dev_read_resources(struct device *dev)
428 pci_read_bases(dev, 6);
429 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
432 void pci_bus_read_resources(struct device *dev)
434 pci_bridge_read_bases(dev);
435 pci_read_bases(dev, 2);
436 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
439 static void pci_set_resource(struct device *dev, struct resource *resource)
441 resource_t base, end;
443 /* Make certain the resource has actually been set */
444 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
445 printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n",
446 dev_path(dev), resource->index,
447 resource_type(resource),
452 /* If I have already stored this resource don't worry about it */
453 if (resource->flags & IORESOURCE_STORED) {
457 /* If the resources is substractive don't worry about it */
458 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
462 /* Only handle PCI memory and IO resources for now */
463 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
466 /* Enable the resources in the command register */
467 if (resource->size) {
468 if (resource->flags & IORESOURCE_MEM) {
469 dev->command |= PCI_COMMAND_MEMORY;
471 if (resource->flags & IORESOURCE_IO) {
472 dev->command |= PCI_COMMAND_IO;
474 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
475 dev->command |= PCI_COMMAND_MASTER;
478 /* Get the base address */
479 base = resource->base;
482 end = resource_end(resource);
484 /* Now store the resource */
485 resource->flags |= IORESOURCE_STORED;
486 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
487 unsigned long base_lo, base_hi;
489 * some chipsets allow us to set/clear the IO bit.
490 * (e.g. VIA 82c686a.) So set it to be safe)
492 base_lo = base & 0xffffffff;
493 base_hi = (base >> 32) & 0xffffffff;
494 if (resource->flags & IORESOURCE_IO) {
495 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
497 pci_write_config32(dev, resource->index, base_lo);
498 if (resource->flags & IORESOURCE_PCI64) {
499 pci_write_config32(dev, resource->index + 4, base_hi);
502 else if (resource->index == PCI_IO_BASE) {
503 /* set the IO ranges */
504 compute_allocate_resource(&dev->link[0], resource,
505 IORESOURCE_IO, IORESOURCE_IO);
506 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
507 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
508 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
509 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
511 else if (resource->index == PCI_MEMORY_BASE) {
512 /* set the memory range */
513 compute_allocate_resource(&dev->link[0], resource,
514 IORESOURCE_MEM | IORESOURCE_PREFETCH,
516 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
517 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
519 else if (resource->index == PCI_PREF_MEMORY_BASE) {
520 /* set the prefetchable memory range */
521 compute_allocate_resource(&dev->link[0], resource,
522 IORESOURCE_MEM | IORESOURCE_PREFETCH,
523 IORESOURCE_MEM | IORESOURCE_PREFETCH);
524 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
525 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
526 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
527 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
530 /* Don't let me think I stored the resource */
531 resource->flags &= ~IORESOURCE_STORED;
532 printk_err("ERROR: invalid resource->index %x\n",
535 report_resource_stored(dev, resource, "");
539 void pci_dev_set_resources(struct device *dev)
541 struct resource *resource, *last;
545 last = &dev->resource[dev->resources];
547 for(resource = &dev->resource[0]; resource < last; resource++) {
548 pci_set_resource(dev, resource);
550 for(link = 0; link < dev->links; link++) {
552 bus = &dev->link[link];
554 assign_resources(bus);
558 /* set a default latency timer */
559 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
561 /* set a default secondary latency timer */
562 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
563 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
566 /* zero the irq settings */
567 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
569 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
571 /* set the cache line size, so far 64 bytes is good for everyone */
572 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
575 void pci_dev_enable_resources(struct device *dev)
577 const struct pci_operations *ops;
580 /* Set the subsystem vendor and device id for mainboard devices */
582 if (dev->on_mainboard && ops && ops->set_subsystem) {
583 printk_debug("%s subsystem <- %02x/%02x\n",
585 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
586 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
587 ops->set_subsystem(dev,
588 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
589 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
591 command = pci_read_config16(dev, PCI_COMMAND);
592 command |= dev->command;
593 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
594 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
595 pci_write_config16(dev, PCI_COMMAND, command);
598 void pci_bus_enable_resources(struct device *dev)
601 /* enable IO in command register if there is VGA card
602 * connected with (even it does not claim IO resource) */
603 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
604 dev->command |= PCI_COMMAND_IO;
605 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
606 ctrl |= dev->link[0].bridge_ctrl;
607 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
608 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
609 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
611 pci_dev_enable_resources(dev);
613 enable_childrens_resources(dev);
616 void pci_bus_reset(struct bus *bus)
619 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
620 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
621 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
623 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
624 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
628 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
630 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
631 ((device & 0xffff) << 16) | (vendor & 0xffff));
634 void pci_dev_init(struct device *dev)
636 #if CONFIG_PCI_ROM_RUN == 1
637 struct rom_header *rom, *ram;
639 rom = pci_rom_probe(dev);
642 ram = pci_rom_load(dev, rom);
650 /** Default device operation for PCI devices */
651 static struct pci_operations pci_dev_ops_pci = {
652 .set_subsystem = pci_dev_set_subsystem,
655 struct device_operations default_pci_ops_dev = {
656 .read_resources = pci_dev_read_resources,
657 .set_resources = pci_dev_set_resources,
658 .enable_resources = pci_dev_enable_resources,
659 .init = pci_dev_init,
662 .ops_pci = &pci_dev_ops_pci,
665 /** Default device operations for PCI bridges */
666 static struct pci_operations pci_bus_ops_pci = {
670 struct device_operations default_pci_ops_bus = {
671 .read_resources = pci_bus_read_resources,
672 .set_resources = pci_dev_set_resources,
673 .enable_resources = pci_bus_enable_resources,
675 .scan_bus = pci_scan_bridge,
677 .reset_bus = pci_bus_reset,
678 .ops_pci = &pci_bus_ops_pci,
682 * @brief Detect the type of downstream bridge
684 * This function is a heuristic to detect which type
685 * of bus is downstream of a pci to pci bridge. This
686 * functions by looking for various capability blocks
687 * to figure out the type of downstream bridge. PCI-X
688 * PCI-E, and Hypertransport all seem to have appropriate
691 * When only a PCI-Express capability is found the type
692 * is examined to see which type of bridge we have.
696 * @return appropriate bridge operations
698 static struct device_operations *get_pci_bridge_ops(device_t dev)
702 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
703 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
705 printk_debug("%s subbordinate bus PCI-X\n", dev_path(dev));
706 return &default_pcix_ops_bus;
709 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
710 /* How do I detect an PCI to AGP bridge? */
712 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
714 while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
716 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
717 if ((flags >> 13) == 1) {
718 /* Host or Secondary Interface */
719 printk_debug("%s subbordinate bus Hypertransport\n",
721 return &default_ht_ops_bus;
725 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
726 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
729 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
730 switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
731 case PCI_EXP_TYPE_ROOT_PORT:
732 case PCI_EXP_TYPE_UPSTREAM:
733 case PCI_EXP_TYPE_DOWNSTREAM:
734 printk_debug("%s subbordinate bus PCI Express\n",
736 return &default_pciexp_ops_bus;
737 case PCI_EXP_TYPE_PCI_BRIDGE:
738 printk_debug("%s subbordinate PCI\n",
740 return &default_pci_ops_bus;
746 return &default_pci_ops_bus;
750 * @brief Set up PCI device operation
757 static void set_pci_ops(struct device *dev)
759 struct pci_driver *driver;
764 /* Look through the list of setup drivers and find one for
767 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
768 if ((driver->vendor == dev->vendor) &&
769 (driver->device == dev->device))
771 dev->ops = driver->ops;
772 printk_spew("%s [%04x/%04x] %sops\n",
774 driver->vendor, driver->device,
775 (driver->ops->scan_bus?"bus ":""));
780 /* If I don't have a specific driver use the default operations */
781 switch(dev->hdr_type & 0x7f) { /* header type */
782 case PCI_HEADER_TYPE_NORMAL: /* standard header */
783 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
785 dev->ops = &default_pci_ops_dev;
787 case PCI_HEADER_TYPE_BRIDGE:
788 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
790 dev->ops = get_pci_bridge_ops(dev);
792 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
793 case PCI_HEADER_TYPE_CARDBUS:
794 dev->ops = &default_cardbus_ops_bus;
800 printk_err("%s [%04x/%04x/%06x] has unknown header "
801 "type %02x, ignoring.\n",
803 dev->vendor, dev->device,
804 dev->class >> 8, dev->hdr_type);
813 * @brief See if we have already allocated a device structure for a given devfn.
815 * Given a linked list of PCI device structures and a devfn number, find the
816 * device structure correspond to the devfn, if present. This function also
817 * removes the device structure from the linked list.
819 * @param list the device structure list
820 * @param devfn a device/function number
822 * @return pointer to the device structure found or null of we have not
823 * allocated a device for this devfn yet.
825 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
829 for(; *list; list = &(*list)->sibling) {
830 if ((*list)->path.type != DEVICE_PATH_PCI) {
831 printk_err("child %s not a pci device\n",
835 if ((*list)->path.u.pci.devfn == devfn) {
836 /* Unlink from the list */
838 *list = (*list)->sibling;
843 /* Just like alloc_dev add the device to the list of device on the bus.
844 * When the list of devices was formed we removed all of the parents
845 * children, and now we are interleaving static and dynamic devices in
850 /* Find the last child of our parent */
851 for(child = dev->bus->children; child && child->sibling; ) {
852 child = child->sibling;
854 /* Place the device on the list of children of it's parent. */
856 child->sibling = dev;
858 dev->bus->children = dev;
866 * @brief Scan a PCI bus.
868 * Determine the existence of a given PCI device.
870 * @param bus pointer to the bus structure
871 * @param devfn to look at
873 * @return The device structure for hte device (if found)
874 * or the NULL if no device is found.
876 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
881 /* Detect if a device is present */
885 dummy.path.type = DEVICE_PATH_PCI;
886 dummy.path.u.pci.devfn = devfn;
887 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
888 /* Have we found somthing?
889 * Some broken boards return 0 if a slot is empty.
891 if ( (id == 0xffffffff) || (id == 0x00000000) ||
892 (id == 0x0000ffff) || (id == 0xffff0000))
894 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
897 dev = alloc_dev(bus, &dummy.path);
900 /* Enable/disable the device. Once we have
901 * found the device specific operations this
902 * operations we will disable the device with
905 * This is geared toward devices that have subfunctions
906 * that do not show up by default.
908 * If a device is a stuff option on the motherboard
909 * it may be absent and enable_dev must cope.
912 /* Run the magice enable sequence for the device */
913 if (dev->chip_ops && dev->chip_ops->enable_dev) {
914 dev->chip_ops->enable_dev(dev);
916 /* Now read the vendor and device id */
917 id = pci_read_config32(dev, PCI_VENDOR_ID);
920 /* If the device does not have a pci id disable it.
921 * Possibly this is because we have already disabled
922 * the device. But this also handles optional devices
923 * that may not always show up.
925 /* If the chain is fully enumerated quit */
926 if ( (id == 0xffffffff) || (id == 0x00000000) ||
927 (id == 0x0000ffff) || (id == 0xffff0000))
930 printk_info("Disabling static device: %s\n",
937 /* Read the rest of the pci configuration information */
938 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
939 class = pci_read_config32(dev, PCI_CLASS_REVISION);
941 /* Store the interesting information in the device structure */
942 dev->vendor = id & 0xffff;
943 dev->device = (id >> 16) & 0xffff;
944 dev->hdr_type = hdr_type;
945 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
946 dev->class = class >> 8;
949 /* Architectural/System devices always need to
952 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
953 dev->command |= PCI_COMMAND_MASTER;
955 /* Look at the vendor and device id, or at least the
956 * header type and class and figure out which set of
957 * configuration methods to use. Unless we already
962 /* Now run the magic enable/disable sequence for the device */
963 if (dev->ops && dev->ops->enable) {
964 dev->ops->enable(dev);
968 /* Display the device and error if we don't have some pci operations
971 printk_debug("%s [%04x/%04x] %s%s\n",
973 dev->vendor, dev->device,
974 dev->enabled?"enabled": "disabled",
975 dev->ops?"" : " No operations"
982 * @brief Scan a PCI bus.
984 * Determine the existence of devices and bridges on a PCI bus. If there are
985 * bridges on the bus, recursively scan the buses behind the bridges.
987 * This function is the default scan_bus() method for the root device
990 * @param bus pointer to the bus structure
991 * @param min_devfn minimum devfn to look at in the scan usually 0x00
992 * @param max_devfn maximum devfn to look at in the scan usually 0xff
993 * @param max current bus number
995 * @return The maximum bus number found, after scanning all subordinate busses
997 unsigned int pci_scan_bus(struct bus *bus,
998 unsigned min_devfn, unsigned max_devfn,
1002 device_t old_devices;
1005 #if PCI_BUS_SEGN_BITS
1006 printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
1008 printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1011 old_devices = bus->children;
1015 /* probe all devices/functions on this bus with some optimization for
1016 * non-existence and single funcion devices
1018 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1021 /* First thing setup the device structure */
1022 dev = pci_scan_get_dev(&old_devices, devfn);
1024 /* See if a device is present and setup the device
1027 dev = pci_probe_dev(dev, bus, devfn);
1029 /* if this is not a multi function device,
1030 * or the device is not present don't waste
1031 * time probing another function.
1032 * Skip to next device.
1034 if ((PCI_FUNC(devfn) == 0x00) &&
1035 (!dev || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80))))
1042 /* Die if any leftover Static devices are are found.
1043 * There's probably a problem in the Config.lb.
1047 for(left = old_devices; left; left = left->sibling) {
1048 printk_err("%s\n", dev_path(left));
1050 die("PCI: Left over static devices. Check your Config.lb\n");
1053 /* For all children that implement scan_bus (i.e. bridges)
1054 * scan the bus behind that child.
1056 for(child = bus->children; child; child = child->sibling) {
1057 max = scan_bus(child, max);
1061 * We've scanned the bus and so we know all about what's on
1062 * the other side of any bridges that may be on this bus plus
1065 * Return how far we've got finding sub-buses.
1067 printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
1074 * @brief Scan a PCI bridge and the buses behind the bridge.
1076 * Determine the existence of buses behind the bridge. Set up the bridge
1077 * according to the result of the scan.
1079 * This function is the default scan_bus() method for PCI bridge devices.
1081 * @param dev pointer to the bridge device
1082 * @param max the highest bus number assgined up to now
1084 * @return The maximum bus number found, after scanning all subordinate busses
1086 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1087 unsigned int (*do_scan_bus)(struct bus *bus,
1088 unsigned min_devfn, unsigned max_devfn, unsigned int max))
1094 printk_spew("%s for %s\n", __func__, dev_path(dev));
1096 bus = &dev->link[0];
1100 /* Set up the primary, secondary and subordinate bus numbers. We have
1101 * no idea how many buses are behind this bridge yet, so we set the
1102 * subordinate bus number to 0xff for the moment.
1104 bus->secondary = ++max;
1105 bus->subordinate = 0xff;
1107 /* Clear all status bits and turn off memory, I/O and master enables. */
1108 cr = pci_read_config16(dev, PCI_COMMAND);
1109 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1110 pci_write_config16(dev, PCI_STATUS, 0xffff);
1113 * Read the existing primary/secondary/subordinate bus
1114 * number configuration.
1116 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1118 /* Configure the bus numbers for this bridge: the configuration
1119 * transactions will not be propagated by the bridge if it is not
1120 * correctly configured.
1122 buses &= 0xff000000;
1123 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
1124 ((unsigned int) (bus->secondary) << 8) |
1125 ((unsigned int) (bus->subordinate) << 16));
1126 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1128 /* Now we can scan all subordinate buses
1129 * i.e. the bus behind the bridge.
1131 max = do_scan_bus(bus, 0x00, 0xff, max);
1133 /* We know the number of buses behind this bridge. Set the subordinate
1134 * bus number to its real value.
1136 bus->subordinate = max;
1137 buses = (buses & 0xff00ffff) |
1138 ((unsigned int) (bus->subordinate) << 16);
1139 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1140 pci_write_config16(dev, PCI_COMMAND, cr);
1142 printk_spew("%s returns max %d\n", __func__, max);
1147 * @brief Scan a PCI bridge and the buses behind the bridge.
1149 * Determine the existence of buses behind the bridge. Set up the bridge
1150 * according to the result of the scan.
1152 * This function is the default scan_bus() method for PCI bridge devices.
1154 * @param dev pointer to the bridge device
1155 * @param max the highest bus number assgined up to now
1157 * @return The maximum bus number found, after scanning all subordinate busses
1159 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1161 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1165 Tell the EISA int controller this int must be level triggered
1166 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
1168 void pci_level_irq(unsigned char intNum)
1170 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
1172 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
1173 intBits |= (1 << intNum);
1175 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
1178 outb((unsigned char) intBits, 0x4d0);
1179 outb((unsigned char) (intBits >> 8), 0x4d1);
1181 /* this seems like an error but is not ... */
1183 if (inb(0x4d0) != (intBits & 0xff)) {
1184 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1185 __func__, intBits &0xff, inb(0x4d0));
1187 if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
1188 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1189 __func__, (intBits>>8) &0xff, inb(0x4d1));
1195 This function assigns IRQs for all functions contained within
1196 the indicated device address. If the device does not exist or does
1197 not require interrupts then this function has no effect.
1199 This function should be called for each PCI slot in your system.
1201 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1203 The particular irq #s that are passed in depend on the routing inside
1204 your southbridge and on your motherboard.
1208 void pci_assign_irqs(unsigned bus, unsigned slot,
1209 const unsigned char pIntAtoD[4])
1215 unsigned char readback;
1217 /* Each slot may contain up to eight functions */
1218 for (functNum = 0; functNum < 8; functNum++) {
1219 pdev = dev_find_slot(bus, (slot << 3) + functNum);
1222 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1224 // PCI spec says all other values are reserved
1225 if ((line >= 1) && (line <= 4)) {
1226 irq = pIntAtoD[line - 1];
1228 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1229 irq, bus, slot, functNum);
1231 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1232 pIntAtoD[line - 1]);
1234 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1235 printk_debug(" Readback = %d\n", readback);
1237 // Change to level triggered
1238 pci_level_irq(pIntAtoD[line - 1]);