src/devices/pci_device.c

   1 /*
   2  *      PCI Bus Services, see include/linux/pci.h for further explanation.
   3  *
   4  *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
   5  *      David Mosberger-Tang
   6  *
   7  *      Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
   8  *
   9  *      Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
  10  */
  11
  12 #include <console/console.h>
  13 #include <stdlib.h>
  14 #include <stdint.h>
  15 #include <bitops.h>
  16 #include <string.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20 #include <part/fallback_boot.h>
  21
  22 /** Given a device and register, read the size of the BAR for that register.
  23  * @param dev       Pointer to the device structure
  24  * @param resource  Pointer to the resource structure
  25  * @param index     Address of the pci configuration register
  26  */
  27 static void pci_get_resource(struct device *dev, struct resource *resource, unsigned long index)
  28 {
  29         uint32_t addr, size, base;
  30         unsigned long type;
  31
  32         /* Initialize the resources to nothing */
  33         resource->base = 0;
  34         resource->size = 0;
  35         resource->align = 0;
  36         resource->gran = 0;
  37         resource->limit = 0;
  38         resource->flags = 0;
  39         resource->index = index;
  40
  41         addr = pci_read_config32(dev, index);
  42         if (addr == 0xffffffffUL)
  43                 return;
  44
  45         /* FIXME: more consideration for 64-bit PCI devices,
  46          * we currently detect their size but otherwise
  47          * treat them as 32-bit resources
  48          */
  49         /* get the size */
  50         pci_write_config32(dev, index, ~0);
  51         size = pci_read_config32(dev,  index);
  52
  53         /* get the minimum value the bar can be set to */
  54         pci_write_config32(dev, index, 0);
  55         base = pci_read_config32(dev, index);
  56
  57         /* restore addr */
  58         pci_write_config32(dev, index, addr);
  59
  60         /*
  61          * some broken hardware has read-only registers that do not
  62          * really size correctly. You can tell this if addr == size
  63          * Example: the acer m7229 has BARs 1-4 normally read-only.
  64          * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
  65          * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
  66          * violation of the spec.
  67          * We catch this case and ignore it by settting size and type to 0.
  68          * This incidentally catches the common case where registers
  69          * read back as 0 for both address and size.
  70          */
  71         if ((addr == size) && (addr == base)) {
  72                 if (size != 0) {
  73                         printk_debug(
  74                                 "PCI: %02x:%02x.%01x register %02x(%08x), read-only ignoring it\n",
  75                                 dev->bus->secondary,
  76                                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
  77                                 index, addr);
  78                 }
  79                 resource->flags = 0;
  80         }
  81         /* Now compute the actual size, See PCI Spec 6.2.5.1 ...  */
  82         else if (size & PCI_BASE_ADDRESS_SPACE_IO) {
  83                 type = size & (~PCI_BASE_ADDRESS_IO_MASK);
  84                 /* BUG! Top 16 bits can be zero (or not)
  85                  * So set them to 0xffff so they go away ...
  86                  */
  87                 resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1;
  88                 resource->align = log2(resource->size);
  89                 resource->gran = resource->align;
  90                 resource->flags = IORESOURCE_IO;
  91                 resource->limit = 0xffff;
  92         }
  93         else {
  94                 /* A Memory mapped base address */
  95                 type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
  96                 resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1;
  97                 resource->align = log2(resource->size);
  98                 resource->gran = resource->align;
  99                 resource->flags = IORESOURCE_MEM;
 100                 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 101                         resource->flags |= IORESOURCE_PREFETCH;
 102                 }
 103                 type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 104                 if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) {
 105                         /* 32bit limit */
 106                         resource->limit = 0xffffffffUL;
 107                 }
 108                 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) {
 109                         /* 1MB limit */
 110                         resource->limit = 0x000fffffUL;
 111                 }
 112                 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
 113                         unsigned long index_hi;
 114                         /* 64bit limit
 115                          * For now just treat this as a 32bit limit
 116                          */
 117                         index_hi = index + 4;
 118                         resource->limit = 0xffffffffUL;
 119                         resource->flags |= IORESOURCE_PCI64;
 120                         addr = pci_read_config32( dev, index_hi);
 121                         /* get the extended size */
 122                         pci_write_config32(dev, index_hi, 0xffffffffUL);
 123                         size = pci_read_config32( dev, index_hi);
 124
 125                         /* get the minimum value the bar can be set to */
 126                         pci_write_config32(dev, index_hi, 0);
 127                         base = pci_read_config32(dev,  index_hi);
 128
 129                         /* restore addr */
 130                         pci_write_config32(dev, index_hi, addr);
 131
 132                         if ((size == 0xffffffff) && (base == 0)) {
 133                                 /* Clear the top half of the bar */
 134                                 pci_write_config32(dev, index_hi, 0);
 135                         }
 136                         else {
 137                                 printk_err("PCI: %02x:%02x.%01x Unable to handle 64-bit address\n",
 138                                         dev->bus->secondary,
 139                                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 140                                 resource->flags = IORESOURCE_PCI64;
 141                         }
 142                 }
 143                 else {
 144                         /* Invalid value */
 145                         resource->flags = 0;
 146                 }
 147         }
 148         /* dev->size holds the flags... */
 149         return;
 150 }
 151
 152 /** Read the base address registers for a given device.
 153  * @param dev Pointer to the dev structure
 154  * @param howmany How many registers to read (6 for device, 2 for bridge)
 155  */
 156 static void pci_read_bases(struct device *dev, unsigned int howmany)
 157 {
 158         unsigned int reg;
 159         unsigned long index;
 160
 161         reg = dev->resources;
 162         for(index = PCI_BASE_ADDRESS_0;
 163             (reg < MAX_RESOURCES) && (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
 164                 struct resource *resource;
 165                 resource = &dev->resource[reg];
 166                 pci_get_resource(dev, resource, index);
 167                 reg += (resource->flags & (IORESOURCE_IO | IORESOURCE_MEM))? 1:0;
 168                 index += (resource->flags & IORESOURCE_PCI64)?8:4;
 169         }
 170         dev->resources = reg;
 171 }
 172
 173
 174 static void pci_bridge_read_bases(struct device *dev)
 175 {
 176         unsigned int reg = dev->resources;
 177
 178         /* FIXME handle bridges without some of the optional resources */
 179
 180         /* Initialize the io space constraints on the current bus */
 181         dev->resource[reg].base  = 0;
 182         dev->resource[reg].size  = 0;
 183         dev->resource[reg].align = log2(PCI_IO_BRIDGE_ALIGN);
 184         dev->resource[reg].gran  = log2(PCI_IO_BRIDGE_ALIGN);
 185         dev->resource[reg].limit = 0xffffUL;
 186         dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_PCI_BRIDGE;
 187         dev->resource[reg].index = PCI_IO_BASE;
 188         compute_allocate_resource(dev, &dev->resource[reg],
 189                 IORESOURCE_IO, IORESOURCE_IO);
 190         reg++;
 191
 192         /* Initiliaze the prefetchable memory constraints on the current bus */
 193         dev->resource[reg].base = 0;
 194         dev->resource[reg].size = 0;
 195         dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
 196         dev->resource[reg].gran  = log2(PCI_MEM_BRIDGE_ALIGN);
 197         dev->resource[reg].limit = 0xffffffffUL;
 198         dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE;
 199         dev->resource[reg].index = PCI_PREF_MEMORY_BASE;
 200         compute_allocate_resource(dev, &dev->resource[reg],
 201                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 202                 IORESOURCE_MEM | IORESOURCE_PREFETCH);
 203         reg++;
 204
 205         /* Initialize the memory resources on the current bus */
 206         dev->resource[reg].base = 0;
 207         dev->resource[reg].size = 0;
 208         dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
 209         dev->resource[reg].gran  = log2(PCI_MEM_BRIDGE_ALIGN);
 210         dev->resource[reg].limit = 0xffffffffUL;
 211         dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE;
 212         dev->resource[reg].index = PCI_MEMORY_BASE;
 213         compute_allocate_resource(dev, &dev->resource[reg],
 214                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 215                 IORESOURCE_MEM);
 216         reg++;
 217
 218         dev->resources = reg;
 219 }
 220
 221
 222 void pci_dev_read_resources(struct device *dev)
 223 {
 224         uint32_t addr;
 225         dev->resources = 0;
 226         memset(&dev->resource[0], 0, sizeof(dev->resource));
 227         pci_read_bases(dev, 6);
 228         addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
 229         dev->rom_address = (addr == 0xffffffff)? 0 : addr;
 230 }
 231
 232 void pci_bus_read_resources(struct device *dev)
 233 {
 234         uint32_t addr;
 235         dev->resources = 0;
 236         memset(&dev->resource[0], 0, sizeof(dev->resource));
 237         pci_bridge_read_bases(dev);
 238         pci_read_bases(dev, 2);
 239
 240         addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
 241         dev->rom_address = (addr == 0xffffffff)? 0 : addr;
 242
 243 }
 244
 245
 246 static void pci_set_resource(struct device *dev, struct resource *resource)
 247 {
 248         unsigned long base, limit;
 249         unsigned long bridge_align = PCI_MEM_BRIDGE_ALIGN;
 250         unsigned char buf[10];
 251
 252         /* Make certain the resource has actually been set */
 253         if (!(resource->flags & IORESOURCE_SET)) {
 254 #if 1
 255                 printk_err("ERROR: %02x:%02x.%01x %02x not allocated\n",
 256                         dev->bus->secondary,
 257                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 258                         resource->index);
 259 #endif
 260                 return;
 261         }
 262
 263         /* Only handle PCI memory and IO resources for now */
 264         if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
 265                 return;
 266
 267         if (resource->flags & IORESOURCE_MEM) {
 268                 dev->command |= PCI_COMMAND_MEMORY;
 269                 bridge_align = PCI_MEM_BRIDGE_ALIGN;
 270         }
 271         if (resource->flags & IORESOURCE_IO) {
 272                 dev->command |= PCI_COMMAND_IO;
 273                 bridge_align = PCI_IO_BRIDGE_ALIGN;
 274         }
 275         if (resource->flags & IORESOURCE_PCI_BRIDGE) {
 276                 dev->command |= PCI_COMMAND_MASTER;
 277         }
 278         /* Get the base address */
 279         base = resource->base;
 280
 281         /* Get the limit (rounded up) */
 282         limit = base + ((resource->size + bridge_align - 1UL) & ~(bridge_align -1)) -1UL;
 283
 284         if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 285                 /*
 286                  * some chipsets allow us to set/clear the IO bit.
 287                  * (e.g. VIA 82c686a.) So set it to be safe)
 288                  */
 289                 limit = base + resource->size -1;
 290                 if (resource->flags & IORESOURCE_IO) {
 291                         base |= PCI_BASE_ADDRESS_SPACE_IO;
 292                 }
 293                 pci_write_config32(dev, resource->index, base & 0xffffffff);
 294                 if (resource->flags & IORESOURCE_PCI64) {
 295                         /* FIXME handle real 64bit base addresses */
 296                         pci_write_config32(dev, resource->index + 4, 0);
 297                 }
 298         }
 299         else if (resource->index == PCI_IO_BASE) {
 300                 /* set the IO ranges
 301                  * WARNING: we don't really do 32-bit addressing for IO yet!
 302                  */
 303                 compute_allocate_resource(dev, resource,
 304                         IORESOURCE_IO, IORESOURCE_IO);
 305                 pci_write_config8(dev, PCI_IO_BASE,  base >> 8);
 306                 pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
 307                 pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0);
 308                 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0);
 309         }
 310         else if (resource->index == PCI_MEMORY_BASE) {
 311                 /* set the memory range
 312                  */
 313                 compute_allocate_resource(dev, resource,
 314                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 315                         IORESOURCE_MEM);
 316                 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
 317                 pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
 318         }
 319         else if (resource->index == PCI_PREF_MEMORY_BASE) {
 320                 /* set the prefetchable memory range
 321                  * WARNING: we don't really do 64-bit addressing for prefetchable memory yet!
 322                  */
 323                 compute_allocate_resource(dev, resource,
 324                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 325                         IORESOURCE_MEM | IORESOURCE_PREFETCH);
 326                 pci_write_config16(dev, PCI_PREF_MEMORY_BASE,  base >> 16);
 327                 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
 328                 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0);
 329                 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0);
 330         }
 331         else {
 332                 printk_err("ERROR: invalid resource->index %x\n",
 333                         resource->index);
 334         }
 335         buf[0] = '\0';
 336         if (resource->flags & IORESOURCE_PCI_BRIDGE) {
 337                 sprintf(buf, "bus %d ", dev->secondary);
 338         }
 339
 340         printk_debug(
 341                 "PCI: %02x:%02x.%01x %02x <- [0x%08lx - 0x%08lx] %s%s\n",
 342                 dev->bus->secondary,
 343                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 344                 resource->index,
 345                 resource->base, limit,
 346                 buf,
 347                 (resource->flags & IORESOURCE_IO)? "io":
 348                 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
 349         return;
 350 }
 351
 352 void pci_dev_set_resources(struct device *dev)
 353 {
 354         struct resource *resource, *last;
 355         uint8_t line;
 356
 357         last = &dev->resource[dev->resources];
 358
 359         for(resource = &dev->resource[0]; resource < last; resource++) {
 360                 pci_set_resource(dev, resource);
 361         }
 362         if (dev->children) {
 363                 assign_resources(dev);
 364         }
 365
 366         /* set a default latency timer */
 367         pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 368
 369         /* set a default secondary latency timer */
 370         if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
 371                 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
 372         }
 373
 374         /* zero the irq settings */
 375         line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
 376         if (line) {
 377                 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 378         }
 379         /* set the cache line size, so far 64 bytes is good for everyone */
 380         pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 381 }
 382
 383 struct device_operations default_pci_ops_dev = {
 384         .read_resources = pci_dev_read_resources,
 385         .set_resources = pci_dev_set_resources,
 386         .init = 0,
 387         .scan_bus = 0,
 388 };
 389 struct device_operations default_pci_ops_bus = {
 390         .read_resources = pci_bus_read_resources,
 391         .set_resources = pci_dev_set_resources,
 392         .init = 0,
 393         .scan_bus = pci_scan_bridge,
 394 };
 395 static void set_pci_ops(struct device *dev)
 396 {
 397         struct pci_driver *driver;
 398         if (dev->ops) {
 399                 return;
 400         }
 401         /* Look through the list of setup drivers and find one for
 402          * this pci device
 403          */
 404         for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
 405                 if ((driver->vendor == dev->vendor) &&
 406                         (driver->device == dev->device)) {
 407                         dev->ops = driver->ops;
 408 #if 1
 409                         printk_debug("PCI: %02x:%02x.%01x [%04x/%04x] ops\n",
 410                                 dev->bus->secondary,
 411                                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 412                                 driver->vendor, driver->device
 413                                 );
 414 #endif
 415                         return;
 416                 }
 417         }
 418         /* If I don't have a specific driver use the default operations */
 419         switch(dev->hdr_type & 0x7f) {  /* header type */
 420         case PCI_HEADER_TYPE_NORMAL:    /* standard header */
 421                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 422                         goto bad;
 423                 dev->ops = &default_pci_ops_dev;
 424                 break;
 425         case PCI_HEADER_TYPE_BRIDGE:
 426                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 427                         goto bad;
 428                 dev->ops = &default_pci_ops_bus;
 429                 break;
 430         default:
 431         bad:
 432                 printk_err("PCI: %02x:%02x.%01x [%04x/%04x/%06x] has unknown header "
 433                         "type %02x, ignoring.\n",
 434                         dev->bus->secondary,
 435                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 436                         dev->vendor, dev->device,
 437                         dev->class >> 8, dev->hdr_type);
 438         }
 439         return;
 440 }
 441
 442 /**
 443  * Given a bus and a devfn number, find the device structure
 444  * @param bus The bus structure
 445  * @param devfn a device/function number
 446  * @return pointer to the device structure
 447  */
 448 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
 449 {
 450         struct device *dev = 0;
 451         for(; *list; list = &(*list)->sibling) {
 452                 if ((*list)->devfn == devfn) {
 453                         /* Unlink from the list */
 454                         dev = *list;
 455                         *list = (*list)->sibling;
 456                         dev->sibling = 0;
 457                         break;
 458                 }
 459         }
 460         return dev;
 461 }
 462
 463 void assign_id_set_links(device_t dev, uint8_t *pos,
 464                 uint8_t *previous_pos, unsigned previous_unitid,
 465                 unsigned last_unitid, int *reset_needed,
 466                 struct device *bus, unsigned *next_unitid)
 467 {
 468         static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
 469         static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
 470         uint16_t flags;
 471         struct device last, prev_bus, previous;
 472         unsigned count;
 473         uint8_t present_width_cap;
 474         uint16_t present_freq_cap;
 475         uint8_t upstream_width_cap;
 476         uint16_t upstream_freq_cap;
 477         uint8_t ln_upstream_width_in, ln_present_width_in;
 478         uint8_t ln_upstream_width_out, ln_present_width_out;
 479         uint16_t mask;
 480         uint8_t freq;
 481         uint8_t old_freq;
 482         uint8_t upstream_width, present_width;
 483         uint8_t old_width;
 484
 485         flags = pci_read_config16(dev, (*pos) + PCI_CAP_FLAGS);
 486         printk_debug("flags: 0x%04x\n", (unsigned)flags);
 487         if ((flags >> 13) != 0)
 488                 return; /* Entry is a Host */
 489         /* Entry is a Slave secondary */
 490         flags &= ~0x1f; /* mask out base unit ID */
 491         flags |= *next_unitid & 0x1f; /* assign ID */
 492         count = (flags >> 5) & 0x1f; /* get unit count */
 493         printk_debug("unitid: 0x%02x, count: 0x%02x\n",
 494                 *next_unitid, count);
 495         pci_write_config16(dev, (*pos) + PCI_CAP_FLAGS, flags);
 496         *next_unitid += count;
 497         if (previous_unitid == 0) { /* the link is back to the host */
 498                 prev_bus.secondary = 0;
 499                 /* calculate the previous pos for the host */
 500                 *previous_pos = 0x80;
 501                 previous.bus = &prev_bus;
 502                 previous.devfn = 0x18 << 3;
 503         #warning "FIXME we should not hard code this!"
 504         } else {
 505                 previous.bus = bus;
 506                 previous.devfn = previous_unitid << 3;
 507         }
 508         last.bus = bus;
 509         last.devfn = last_unitid << 3;
 510         /* Set link width and frequency */
 511         present_freq_cap = pci_read_config16(&last,
 512                         (*pos) + PCI_HT_CAP_SLAVE_FREQ_CAP0);
 513         present_width_cap = pci_read_config8(&last,
 514                         (*pos) + PCI_HT_CAP_SLAVE_WIDTH0);
 515         if(previous_unitid == 0) { /* the link is back to the host */
 516                 upstream_freq_cap = pci_read_config16(&previous,
 517                             (*previous_pos) + PCI_HT_CAP_HOST_FREQ_CAP);
 518                 upstream_width_cap = pci_read_config8(&previous,
 519                             (*previous_pos) + PCI_HT_CAP_HOST_WIDTH);
 520         }
 521         else { /* The link is back up the chain */
 522                 upstream_freq_cap = pci_read_config16(&previous,
 523                         (*previous_pos) + PCI_HT_CAP_SLAVE_FREQ_CAP1);
 524                 upstream_width_cap = pci_read_config8(&previous,
 525                         (*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1);
 526         }
 527         /* Calculate the highest possible frequency */
 528         /* Errata for 8131 - freq 5 has hardware problems don't support it */
 529         freq = log2(present_freq_cap & upstream_freq_cap & 0x1f);
 530
 531         /* Calculate the highest width */
 532         ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
 533         ln_present_width_out  = link_width_to_pow2[(present_width_cap >> 4) & 7];
 534         if (ln_upstream_width_in > ln_present_width_out) {
 535                 ln_upstream_width_in = ln_present_width_out;
 536         }
 537         upstream_width = pow2_to_link_width[ln_upstream_width_in];
 538         present_width  = pow2_to_link_width[ln_upstream_width_in] << 4;
 539
 540         ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
 541         ln_present_width_in   = link_width_to_pow2[present_width_cap & 7];
 542         if (ln_upstream_width_out > ln_present_width_in) {
 543                 ln_upstream_width_out = ln_present_width_in;
 544         }
 545         upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
 546         present_width  |= pow2_to_link_width[ln_upstream_width_out];
 547
 548         /* set the present device */
 549         old_freq = pci_read_config8(&last, (*pos) + PCI_HT_CAP_SLAVE_FREQ0);
 550         if(old_freq != freq) {
 551                 pci_write_config8(&last,
 552                                 (*pos) + PCI_HT_CAP_SLAVE_FREQ0, freq);
 553                 *reset_needed = 1;
 554                 printk_debug("HyperT FreqP old %x new %x\n",old_freq,freq);
 555         }
 556         old_width = pci_read_config8(&last,
 557                         (*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1);
 558         if(present_width != old_width) {
 559                 pci_write_config8(&last,
 560                         (*pos) + PCI_HT_CAP_SLAVE_WIDTH0 + 1, present_width);
 561                 *reset_needed = 1;
 562                 printk_debug("HyperT widthP old %x new %x\n",
 563                                 old_width, present_width);
 564         }
 565         /* set the upstream device */
 566         if(previous_unitid == 0) { /* the link is back to the host */
 567                 old_freq = pci_read_config8(&previous,
 568                                 (*previous_pos) + PCI_HT_CAP_HOST_FREQ);
 569                 old_freq &= 0x0f;
 570                 if(freq != old_freq) {
 571                         pci_write_config8(&previous,
 572                             (*previous_pos) + PCI_HT_CAP_HOST_FREQ, freq);
 573                         *reset_needed = 1;
 574                         printk_debug("HyperT freqUH old %x new %x\n",
 575                                         old_freq, freq);
 576                 }
 577                 old_width = pci_read_config8(&previous,
 578                             (*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1);
 579                 if(upstream_width != old_width) {
 580                         pci_write_config8(&previous,
 581                         (*previous_pos) + PCI_HT_CAP_HOST_WIDTH + 1,
 582                                         upstream_width);
 583                         *reset_needed = 1;
 584                         printk_debug("HyperT widthUH old %x new %x\n",
 585                                         old_width, upstream_width);
 586                 }
 587         }
 588         else { /* The link is back up the chain */
 589                 old_freq = pci_read_config8(&previous,
 590                         (*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1);
 591                 old_freq &= 0x0f;
 592                 if(freq != old_freq) {
 593                         pci_write_config8(&previous,
 594                             (*previous_pos) + PCI_HT_CAP_SLAVE_FREQ1,
 595                                 freq);
 596                         *reset_needed = 1;
 597                         printk_debug("HyperT freqUL old %x new %x\n",
 598                                         old_freq, freq);
 599                 }
 600                 old_width = pci_read_config8(&previous,
 601                         (*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1 + 1);
 602                 if(upstream_width != old_width) {
 603                         pci_write_config8(&previous,
 604                             (*previous_pos) + PCI_HT_CAP_SLAVE_WIDTH1,
 605                                         upstream_width);
 606                         *reset_needed = 1;
 607                         printk_debug("HyperT widthUL old %x new %x\n",
 608                                         old_width, upstream_width);
 609                 }
 610         }
 611         *previous_pos = *pos;
 612         *pos=0;
 613 }
 614
 615 #define HYPERTRANSPORT_SUPPORT 1
 616 /** Scan the pci bus devices and bridges.
 617  * @param pci_bus pointer to the bus structure
 618  * @param max current bus number
 619  * @return The maximum bus number found, after scanning all subordinate busses
 620  */
 621 unsigned int pci_scan_bus(struct device *bus, unsigned int max)
 622 {
 623         unsigned int devfn;
 624         struct device *dev, **bus_last;
 625         struct device *old_devices;
 626         struct device *child;
 627 #if HYPERTRANSPORT_SUPPORT
 628         unsigned next_unitid, last_unitid, previous_unitid;
 629         int reset_needed = 0;
 630         uint8_t previous_pos;
 631 #endif
 632
 633         printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
 634
 635         old_devices = bus->children;
 636         bus->children = 0;
 637         bus_last = &bus->children;
 638
 639         post_code(0x24);
 640
 641
 642 #if HYPERTRANSPORT_SUPPORT
 643         /* Spin through the devices and collapse any early
 644          * hypertransport enumeration.
 645          */
 646         for(devfn = 0; devfn <= 0xff; devfn += 8) {
 647                 struct device dummy;
 648                 uint32_t id;
 649                 uint8_t hdr_type, pos;
 650                 dummy.bus = bus;
 651                 dummy.devfn = devfn;
 652                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 653                 if (id == 0xffffffff || id == 0x00000000 ||
 654                         id == 0x0000ffff || id == 0xffff0000) {
 655                         continue;
 656                 }
 657                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 658                 pos = 0;
 659                 switch(hdr_type & 0x7f) {
 660                 case PCI_HEADER_TYPE_NORMAL:
 661                 case PCI_HEADER_TYPE_BRIDGE:
 662                         pos = PCI_CAPABILITY_LIST;
 663                         break;
 664                 }
 665                 if (pos > PCI_CAP_LIST_NEXT) {
 666                         pos = pci_read_config8(&dummy, pos);
 667                 }
 668                 while(pos != 0) {
 669                         uint8_t cap;
 670                         cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
 671                         printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
 672                         if (cap == PCI_CAP_ID_HT) {
 673                                 uint16_t flags;
 674                                 flags = pci_read_config16(&dummy,
 675                                                 pos + PCI_CAP_FLAGS);
 676                                 printk_debug("flags: 0x%04x\n",
 677                                                 (unsigned)flags);
 678                                 if ((flags >> 13) == 0) {
 679                                         /* Clear the unitid */
 680                                         flags &= ~0x1f;
 681                                         pci_write_config16(&dummy,
 682                                                 pos + PCI_CAP_FLAGS, flags);
 683                                         break;
 684                                 }
 685                         }
 686                         pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
 687                 }
 688         }
 689         /* If present assign unitid to a hypertransport chain */
 690         last_unitid = 0;
 691         next_unitid = 1;
 692         previous_pos = 0;
 693         do {
 694                 struct device dummy;
 695                 uint32_t id;
 696                 uint8_t hdr_type, pos;
 697
 698                 previous_unitid = last_unitid;
 699                 last_unitid = next_unitid;
 700
 701                 /* Read the next unassigned device off the stack */
 702                 dummy.bus   = bus;
 703                 dummy.devfn = 0;
 704                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 705                 /* If the chain is enumerated quit */
 706                 if (id == 0xffffffff || id == 0x00000000 ||
 707                         id == 0x0000ffff || id == 0xffff0000) {
 708                         break;
 709                 }
 710                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 711                 pos = 0;
 712                 switch(hdr_type & 0x7f) {
 713                 case PCI_HEADER_TYPE_NORMAL:
 714                 case PCI_HEADER_TYPE_BRIDGE:
 715                         pos = PCI_CAPABILITY_LIST;
 716                         break;
 717                 }
 718                 if (pos > PCI_CAP_LIST_NEXT) {
 719                         pos = pci_read_config8(&dummy, pos);
 720                 }
 721                 while(pos != 0) {   /* loop through the linked list */
 722                         uint8_t cap;
 723                         cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
 724                         printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
 725                         if (cap == PCI_CAP_ID_HT) {
 726                                 assign_id_set_links(&dummy,&pos,&previous_pos,
 727                                                 previous_unitid, last_unitid,
 728                                                 &reset_needed, bus,
 729                                                 &next_unitid);
 730                         }
 731                         if(pos)
 732                                 pos = pci_read_config8(&dummy,
 733                                                 pos + PCI_CAP_LIST_NEXT);
 734                 }
 735         } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
 736 #if HAVE_HARD_RESET == 1
 737         if(reset_needed) {
 738                 printk_debug("HyperT reset needed\n");
 739                 boot_successful();
 740                 hard_reset();
 741         }
 742         printk_debug("HyperT reset not needed\n");
 743 #endif /* HAVE_HARD_RESET */
 744 #endif /* HYPERTRANSPORT_SUPPORT */
 745
 746         /* probe all devices on this bus with some optimization for non-existance and
 747            single funcion devices */
 748         for (devfn = 0; devfn <= 0xff; devfn++) {
 749                 struct device dummy;
 750                 uint32_t id, class;
 751                 uint8_t hdr_type;
 752
 753                 /* First thing setup the device structure */
 754                 dev = pci_scan_get_dev(&old_devices, devfn);
 755
 756                 dummy.bus = bus;
 757                 dummy.devfn = devfn;
 758                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 759                 /* some broken boards return 0 if a slot is empty: */
 760                 if (!dev &&
 761                         (id == 0xffffffff || id == 0x00000000 ||
 762                          id == 0x0000ffff || id == 0xffff0000)) {
 763                         printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
 764                         if (PCI_FUNC(devfn) == 0x00) {
 765                                 /* if this is a function 0 device and it is not present,
 766                                    skip to next device */
 767                                 devfn += 0x07;
 768                         }
 769                         /* multi function device, skip to next function */
 770                         continue;
 771                 }
 772                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 773                 class = pci_read_config32(&dummy, PCI_CLASS_REVISION);
 774
 775                 if (!dev) {
 776                         if ((dev = malloc(sizeof(*dev))) == 0) {
 777                                 printk_err("PCI: out of memory.\n");
 778                                 continue;
 779                         }
 780                         memset(dev, 0, sizeof(*dev));
 781                         dev->bus = bus;
 782                         dev->devfn = devfn;
 783                         dev->vendor = id & 0xffff;
 784                         dev->device = (id >> 16) & 0xffff;
 785                         dev->hdr_type = hdr_type;
 786                         /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
 787                         dev->class = class >> 8;
 788
 789                         /* If we don't have prior information about this device enable it */
 790                         dev->enable = 1;
 791                 }
 792
 793                 /* Look at the vendor and device id, or at least the
 794                  * header type and class and figure out which set of configuration
 795                  * methods to use.
 796                  */
 797                 set_pci_ops(dev);
 798                 /* Kill the device if we don't have some pci operations for it */
 799                 if (!dev->ops) {
 800                         free(dev);
 801                         continue;
 802                 }
 803
 804                 /* Now run the magic enable/disable sequence for the device */
 805                 if (dev->ops && dev->ops->enable) {
 806                         dev->ops->enable(dev);
 807                 }
 808
 809                 printk_debug("PCI: %02x:%02x.%01x [%04x/%04x] %s\n",
 810                         bus->secondary, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 811                         dev->vendor, dev->device,
 812                         dev->enable?"enabled": "disabled");
 813
 814                 /* Put it into the global device chain. */
 815                 append_device(dev);
 816
 817                 /* Now insert it into the list of devices held by the parent bus. */
 818                 *bus_last = dev;
 819                 bus_last = &dev->sibling;
 820
 821                 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
 822                         /* if this is not a multi function device, don't waste time probe
 823                            another function. Skip to next device. */
 824                         devfn += 0x07;
 825                 }
 826         }
 827         post_code(0x25);
 828
 829         for(child = bus->children; child; child = child->sibling) {
 830                 if (!child->ops->scan_bus)
 831                         continue;
 832                 max = child->ops->scan_bus(child, max);
 833
 834         }
 835         /*
 836          * We've scanned the bus and so we know all about what's on
 837          * the other side of any bridges that may be on this bus plus
 838          * any devices.
 839          *
 840          * Return how far we've got finding sub-buses.
 841          */
 842         printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
 843         post_code(0x55);
 844         return max;
 845 }
 846
 847 /** Scan the bus, first for bridges and next for devices.
 848  * @param pci_bus pointer to the bus structure
 849  * @return The maximum bus number found, after scanning all subordinate busses
 850  */
 851 unsigned int pci_scan_bridge(struct device *bus, unsigned int max)
 852 {
 853         uint32_t buses;
 854         uint16_t cr;
 855         /* Set up the primary, secondary and subordinate bus numbers. We have
 856          * no idea how many buses are behind this bridge yet, so we set the
 857          * subordinate bus number to 0xff for the moment
 858          */
 859         bus->secondary = ++max;
 860         bus->subordinate = 0xff;
 861
 862         /* Clear all status bits and turn off memory, I/O and master enables. */
 863         cr = pci_read_config16(bus, PCI_COMMAND);
 864         pci_write_config16(bus, PCI_COMMAND, 0x0000);
 865         pci_write_config16(bus, PCI_STATUS, 0xffff);
 866
 867         /*
 868          * Read the existing primary/secondary/subordinate bus
 869          * number configuration.
 870          */
 871         buses = pci_read_config32(bus, PCI_PRIMARY_BUS);
 872
 873         /* Configure the bus numbers for this bridge: the configuration
 874          * transactions will not be propagated by the bridge if it is not
 875          * correctly configured
 876          */
 877         buses &= 0xff000000;
 878         buses |= (((unsigned int) (bus->bus->secondary) << 0) |
 879                 ((unsigned int) (bus->secondary) << 8) |
 880                 ((unsigned int) (bus->subordinate) << 16));
 881         pci_write_config32(bus, PCI_PRIMARY_BUS, buses);
 882
 883         /* Now we can scan all subordinate buses i.e. the bus hehind the bridge */
 884         max = pci_scan_bus(bus, max);
 885
 886         /* We know the number of buses behind this bridge. Set the subordinate
 887          *  bus number to its real value
 888          */
 889         bus->subordinate = max;
 890         buses = (buses & 0xff00ffff) |
 891                 ((unsigned int) (bus->subordinate) << 16);
 892         pci_write_config32(bus, PCI_PRIMARY_BUS, buses);
 893         pci_write_config16(bus, PCI_COMMAND, cr);
 894
 895         return max;
 896 }
 897
 898
 899 static void pci_root_read_resources(struct device *bus)
 900 {
 901         int res = 0;
 902         /* Initialize the system wide io space constraints */
 903         bus->resource[res].base  = 0x400;
 904         bus->resource[res].size  = 0;
 905         bus->resource[res].align = 0;
 906         bus->resource[res].gran  = 0;
 907         bus->resource[res].limit = 0xffffUL;
 908         bus->resource[res].flags = IORESOURCE_IO;
 909         bus->resource[res].index = PCI_IO_BASE;
 910         compute_allocate_resource(bus, &bus->resource[res],
 911                 IORESOURCE_IO, IORESOURCE_IO);
 912         res++;
 913
 914         /* Initialize the system wide memory resources constraints */
 915         bus->resource[res].base  = 0;
 916         bus->resource[res].size  = 0;
 917         bus->resource[res].align = 0;
 918         bus->resource[res].gran  = 0;
 919         bus->resource[res].limit = 0xffffffffUL;
 920         bus->resource[res].flags = IORESOURCE_MEM;
 921         bus->resource[res].index = PCI_MEMORY_BASE;
 922         compute_allocate_resource(bus, &bus->resource[res],
 923                 IORESOURCE_MEM, IORESOURCE_MEM);
 924         res++;
 925
 926         bus->resources = res;
 927 }
 928 static void pci_root_set_resources(struct device *bus)
 929 {
 930         compute_allocate_resource(bus,
 931                 &bus->resource[0], IORESOURCE_IO, IORESOURCE_IO);
 932         compute_allocate_resource(bus,
 933                 &bus->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
 934         assign_resources(bus);
 935 }
 936
 937 struct device_operations default_pci_ops_root = {
 938         .read_resources = pci_root_read_resources,
 939         .set_resources = pci_root_set_resources,
 940         .init = 0,
 941         .scan_bus = pci_scan_bus,
 942 };
 943