2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <device/chip.h>
22 #include <part/hard_reset.h>
23 #include <part/fallback_boot.h>
25 /** Given a device and register, read the size of the BAR for that register.
26 * @param dev Pointer to the device structure
27 * @param resource Pointer to the resource structure
28 * @param index Address of the pci configuration register
30 static struct resource *pci_get_resource(struct device *dev, unsigned long index)
32 struct resource *resource;
33 uint32_t addr, size, base;
36 /* Initialize the resources to nothing */
37 resource = get_resource(dev, index);
39 addr = pci_read_config32(dev, index);
41 /* FIXME: more consideration for 64-bit PCI devices,
42 * we currently detect their size but otherwise
43 * treat them as 32-bit resources
46 pci_write_config32(dev, index, ~0);
47 size = pci_read_config32(dev, index);
49 /* get the minimum value the bar can be set to */
50 pci_write_config32(dev, index, 0);
51 base = pci_read_config32(dev, index);
54 pci_write_config32(dev, index, addr);
57 * some broken hardware has read-only registers that do not
58 * really size correctly. You can tell this if addr == size
59 * Example: the acer m7229 has BARs 1-4 normally read-only.
60 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
61 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
62 * violation of the spec.
63 * We catch this case and ignore it by settting size and type to 0.
64 * This incidentally catches the common case where registers
65 * read back as 0 for both address and size.
67 if ((addr == size) && (addr == base)) {
70 "%s register %02x(%08x), read-only ignoring it\n",
76 /* Now compute the actual size, See PCI Spec 6.2.5.1 ... */
77 else if (size & PCI_BASE_ADDRESS_SPACE_IO) {
78 type = size & (~PCI_BASE_ADDRESS_IO_MASK);
79 /* BUG! Top 16 bits can be zero (or not)
80 * So set them to 0xffff so they go away ...
82 resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1;
83 resource->align = log2(resource->size);
84 resource->gran = resource->align;
85 resource->flags |= IORESOURCE_IO;
86 resource->limit = 0xffff;
89 /* A Memory mapped base address */
90 type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
91 resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1;
92 resource->align = log2(resource->size);
93 resource->gran = resource->align;
94 resource->flags |= IORESOURCE_MEM;
95 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
96 resource->flags |= IORESOURCE_PREFETCH;
98 type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
99 if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) {
101 resource->limit = 0xffffffffUL;
103 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) {
105 resource->limit = 0x000fffffUL;
107 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
108 unsigned long index_hi;
110 * For now just treat this as a 32bit limit
112 index_hi = index + 4;
113 resource->limit = 0xffffffffUL;
114 resource->flags |= IORESOURCE_PCI64;
115 addr = pci_read_config32( dev, index_hi);
116 /* get the extended size */
117 pci_write_config32(dev, index_hi, 0xffffffffUL);
118 size = pci_read_config32( dev, index_hi);
120 /* get the minimum value the bar can be set to */
121 pci_write_config32(dev, index_hi, 0);
122 base = pci_read_config32(dev, index_hi);
125 pci_write_config32(dev, index_hi, addr);
127 if ((size == 0xffffffff) && (base == 0)) {
128 /* Clear the top half of the bar */
129 pci_write_config32(dev, index_hi, 0);
132 printk_err("%s Unable to handle 64-bit address\n",
134 resource->flags = IORESOURCE_PCI64;
142 /* dev->size holds the flags... */
146 /** Read the base address registers for a given device.
147 * @param dev Pointer to the dev structure
148 * @param howmany How many registers to read (6 for device, 2 for bridge)
150 static void pci_read_bases(struct device *dev, unsigned int howmany)
154 for (index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
155 struct resource *resource;
156 resource = pci_get_resource(dev, index);
157 index += (resource->flags & IORESOURCE_PCI64)?8:4;
159 compact_resources(dev);
162 static void pci_bridge_read_bases(struct device *dev)
164 struct resource *resource;
166 /* FIXME handle bridges without some of the optional resources */
168 /* Initialize the io space constraints on the current bus */
169 resource = get_resource(dev, PCI_IO_BASE);
171 resource->align = log2(PCI_IO_BRIDGE_ALIGN);
172 resource->gran = log2(PCI_IO_BRIDGE_ALIGN);
173 resource->limit = 0xffffUL;
174 resource->flags |= IORESOURCE_IO | IORESOURCE_PCI_BRIDGE;
175 compute_allocate_resource(&dev->link[0], resource,
176 IORESOURCE_IO, IORESOURCE_IO);
178 /* Initiliaze the prefetchable memory constraints on the current bus */
179 resource = get_resource(dev, PCI_PREF_MEMORY_BASE);
181 resource->align = log2(PCI_MEM_BRIDGE_ALIGN);
182 resource->gran = log2(PCI_MEM_BRIDGE_ALIGN);
183 resource->limit = 0xffffffffUL;
184 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE;
185 resource->index = PCI_PREF_MEMORY_BASE;
186 compute_allocate_resource(&dev->link[0], resource,
187 IORESOURCE_MEM | IORESOURCE_PREFETCH,
188 IORESOURCE_MEM | IORESOURCE_PREFETCH);
190 /* Initialize the memory resources on the current bus */
191 resource = get_resource(dev, PCI_MEMORY_BASE);
193 resource->align = log2(PCI_MEM_BRIDGE_ALIGN);
194 resource->gran = log2(PCI_MEM_BRIDGE_ALIGN);
195 resource->limit = 0xffffffffUL;
196 resource->flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE;
197 compute_allocate_resource(&dev->link[0], resource,
198 IORESOURCE_MEM | IORESOURCE_PREFETCH,
201 compact_resources(dev);
204 void pci_dev_read_resources(struct device *dev)
208 pci_read_bases(dev, 6);
210 addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
211 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
214 void pci_bus_read_resources(struct device *dev)
218 pci_bridge_read_bases(dev);
219 pci_read_bases(dev, 2);
221 addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
222 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
226 * @brief round a number up to an alignment.
227 * @param val the starting value
228 * @param roundup Alignment as a power of two
229 * @returns rounded up number
231 static unsigned long round(unsigned long val, unsigned long roundup)
233 /* ROUNDUP MUST BE A POWER OF TWO. */
234 unsigned long inverse;
235 inverse = ~(roundup - 1);
236 val += (roundup - 1);
241 static void pci_set_resource(struct device *dev, struct resource *resource)
243 unsigned long base, limit;
244 unsigned char buf[10];
247 /* Make certain the resource has actually been set */
249 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
250 printk_err("ERROR: %s %02x not allocated\n",
251 dev_path(dev), resource->index);
255 /* If I have already stored this resource don't worry about it */
256 if (resource->flags & IORESOURCE_STORED) {
260 /* Only handle PCI memory and IO resources for now */
261 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
264 if (resource->flags & IORESOURCE_MEM) {
265 dev->command |= PCI_COMMAND_MEMORY;
267 if (resource->flags & IORESOURCE_IO) {
268 dev->command |= PCI_COMMAND_IO;
270 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
271 dev->command |= PCI_COMMAND_MASTER;
274 /* Get the base address */
275 base = resource->base;
277 /* Get the resource granularity */
278 gran = 1UL << resource->gran;
280 /* For a non bridge resource granularity and alignment are the same.
281 * For a bridge resource align is the largest needed alignment below
282 * the bridge. While the granularity is simply how many low bits of the
283 * address cannot be set.
286 /* Get the limit (rounded up) */
287 limit = base + round(resource->size, gran) - 1UL;
289 /* Now store the resource */
290 resource->flags |= IORESOURCE_STORED;
291 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
292 /* some chipsets allow us to set/clear the IO bit.
293 * (e.g. VIA 82c686a.) So set it to be safe) */
294 limit = base + resource->size -1;
295 if (resource->flags & IORESOURCE_IO) {
296 base |= PCI_BASE_ADDRESS_SPACE_IO;
298 pci_write_config32(dev, resource->index, base & 0xffffffff);
299 if (resource->flags & IORESOURCE_PCI64) {
300 /* FIXME handle real 64bit base addresses */
301 pci_write_config32(dev, resource->index + 4, 0);
303 } else if (resource->index == PCI_IO_BASE) {
305 * WARNING: we don't really do 32-bit addressing for IO yet!
307 compute_allocate_resource(&dev->link[0], resource,
308 IORESOURCE_IO, IORESOURCE_IO);
309 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
310 pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
311 pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0);
312 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0);
313 } else if (resource->index == PCI_MEMORY_BASE) {
314 /* set the memory range */
315 compute_allocate_resource(&dev->link[0], resource,
316 IORESOURCE_MEM | IORESOURCE_PREFETCH,
318 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
319 pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
320 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
321 /* set the prefetchable memory range
322 * WARNING: we don't really do 64-bit addressing for
323 * prefetchable memory yet! */
324 compute_allocate_resource(&dev->link[0], resource,
325 IORESOURCE_MEM | IORESOURCE_PREFETCH,
326 IORESOURCE_MEM | IORESOURCE_PREFETCH);
327 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
328 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
329 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0);
330 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0);
332 /* Don't let me think I stored the resource */
333 resource->flags &= ~IORESOURCE_STORED;
334 printk_err("ERROR: invalid resource->index %x\n",
339 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
340 sprintf(buf, "bus %d ", dev->link[0].secondary);
342 printk_debug("%s %02x <- [0x%08lx - 0x%08lx] %s%s\n",
343 dev_path(dev), resource->index, resource->base,
345 (resource->flags & IORESOURCE_IO)? "io":
346 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
350 void pci_dev_set_resources(struct device *dev)
352 struct resource *resource, *last;
356 last = &dev->resource[dev->resources];
357 for (resource = &dev->resource[0]; resource < last; resource++) {
358 pci_set_resource(dev, resource);
361 for (link = 0; link < dev->links; link++) {
363 bus = &dev->link[link];
365 assign_resources(bus);
369 /* set a default latency timer */
370 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
372 /* set a default secondary latency timer */
373 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
374 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
377 /* zero the irq settings */
378 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
380 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
382 /* set the cache line size, so far 64 bytes is good for everyone */
383 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
386 void pci_dev_enable_resources(struct device *dev)
389 command = pci_read_config16(dev, PCI_COMMAND);
390 command |= dev->command;
391 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
392 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
393 pci_write_config16(dev, PCI_COMMAND, command);
395 enable_childrens_resources(dev);
398 void pci_bus_enable_resources(struct device *dev)
401 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
402 ctrl |= dev->link[0].bridge_ctrl;
403 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
404 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
405 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
407 pci_dev_enable_resources(dev);
410 /** Default device operation for PCI devices */
411 struct device_operations default_pci_ops_dev = {
412 .read_resources = pci_dev_read_resources,
413 .set_resources = pci_dev_set_resources,
414 .enable_resources = pci_dev_enable_resources,
419 /** Default device operations for PCI bridges */
420 struct device_operations default_pci_ops_bus = {
421 .read_resources = pci_bus_read_resources,
422 .set_resources = pci_dev_set_resources,
423 .enable_resources = pci_bus_enable_resources,
425 .scan_bus = pci_scan_bridge,
429 * @brief Set up PCI device operation
436 static void set_pci_ops(struct device *dev)
438 struct pci_driver *driver;
444 /* Look through the list of setup drivers and find one for
446 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
447 if ((driver->vendor == dev->vendor) &&
448 (driver->device == dev->device)) {
449 dev->ops = driver->ops;
451 printk_debug("%s [%04x/%04x] %sops\n", dev_path(dev),
452 driver->vendor, driver->device,
453 (driver->ops->scan_bus?"bus ":""));
460 extern struct pci_driver generic_vga_driver;
461 /* TODO: Install generic VGA driver for VGA devices, base on the
463 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
464 printk_debug("setting up generic VGA driver\n");
465 dev->ops = generic_vga_driver.ops;
470 /* If I don't have a specific driver use the default operations */
471 switch(dev->hdr_type & 0x7f) { /* header type */
472 case PCI_HEADER_TYPE_NORMAL: /* standard header */
473 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
475 dev->ops = &default_pci_ops_dev;
477 case PCI_HEADER_TYPE_BRIDGE:
478 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
480 dev->ops = &default_pci_ops_bus;
485 printk_err("%s [%04x/%04x/%06x] has unknown header "
486 "type %02x, ignoring.\n",
488 dev->vendor, dev->device,
489 dev->class >> 8, dev->hdr_type);
496 * @brief Find a specific device structure on a list of device structures
498 * Given a linked list of PCI device structures and a devfn number, find the
499 * device structure correspond to the devfn.
501 * @param list the device structure list
502 * @param devfn a device/function number
504 * @return pointer to the device structure found
506 static struct device *pci_scan_get_dev(struct device **list,
509 struct device *dev = 0;
511 printk_debug("%s, looking for devfn: %02x.%01x\n", __FUNCTION__,
512 devfn >> 3, devfn & 7);
513 for (; *list; list = &(*list)->sibling) {
514 if ((*list)->path.type != DEVICE_PATH_PCI) {
515 printk_err("child %s not a pci device\n",
519 if ((*list)->path.u.pci.devfn == devfn) {
520 /* Unlink from the list */
522 *list = (*list)->sibling;
528 printk_debug("%s, found dev %08x\n", __FUNCTION__, dev);
530 /* FIXME: why are we doing this ? Isn't there some order between the
531 * structures before ? */
534 /* Find the last child of our parent */
535 for (child = dev->bus->children; child && child->sibling; ) {
536 child = child->sibling;
538 /* Place the device on the list of children of it's parent. */
540 child->sibling = dev;
542 dev->bus->children = dev;
550 * @brief Scan a PCI bus
552 * Determine the existence of devices and bridges on a PCI bus. If there are
553 * bridges on the bus, recursively scan the buses behind the bridges.
555 * This function is the default scan_bus() method for the root device
558 * @param bus pointer to the bus structure
559 * @param min_devfn minimum devfn to look at in the scan usually 0x00
560 * @param max_devfn maximum devfn to look at in the scan usually 0xff
561 * @param max current bus number
563 * @return The maximum bus number found, after scanning all subordinate busses
565 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
566 unsigned max_devfn, unsigned int max)
570 device_t old_devices;
573 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
575 old_devices = bus->children;
580 /* probe all devices/functions on this bus with some optimization for
581 * non-existence and single funcion devices */
582 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
586 /* device structures for PCI devices associated with static
587 * devices are already created during the static device
588 * enumeration, find out if it is the case for this devfn */
589 dev = pci_scan_get_dev(&old_devices, devfn);
592 /* it's not associated with a static device, detect if
593 * this device is present */
596 dummy.path.type = DEVICE_PATH_PCI;
597 dummy.path.u.pci.devfn = devfn;
598 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
599 /* some broken boards return 0 if a slot is empty: */
600 if ((id == 0xffffffff) || (id == 0x00000000) ||
601 (id == 0x0000ffff) || (id == 0xffff0000)) {
602 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n",
604 if (PCI_FUNC(devfn) == 0x00) {
605 /* if this is a function 0 device and
606 * it is not present, skip to next
610 /* this function in a multi function device is
611 * not present, skip to next function */
614 dev = alloc_dev(bus, &dummy.path);
616 /* Run the magic enable/disable sequence for the
618 /* FIXME: What happen if this PCI device listed as
619 * static device but does not exist ? This calls
620 * some arbitray code without any justification
621 * Also, it calls the enable function regardlessly
622 * the value of dev->enabled */
623 if (dev->chip && dev->chip->control &&
624 dev->chip->control->enable_dev) {
625 int enabled = dev->enabled;
627 dev->chip->control->enable_dev(dev);
628 dev->enabled = enabled;
630 /* Now read the vendor and device id */
631 id = pci_read_config32(dev, PCI_VENDOR_ID);
633 /* Read the rest of the pci configuration information */
634 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
635 class = pci_read_config32(dev, PCI_CLASS_REVISION);
637 /* Store the interesting information in the device structure */
638 dev->vendor = id & 0xffff;
639 dev->device = (id >> 16) & 0xffff;
640 dev->hdr_type = hdr_type;
641 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
642 dev->class = class >> 8;
644 /* Look at the vendor and device id, or at least the
645 * header type and class and figure out which set of
646 * configuration methods to use. Unless we already
650 /* Error if we don't have some pci operations for it */
652 printk_err("%s No device operations\n",
657 /* Now run the magic enable/disable sequence for the device */
658 if (dev->ops && dev->ops->enable) {
659 dev->ops->enable(dev);
660 } else if (dev->chip && dev->chip->control &&
661 dev->chip->control->enable_dev) {
662 dev->chip->control->enable_dev(dev);
665 printk_debug("%s [%04x/%04x] %s\n",
667 dev->vendor, dev->device,
668 dev->enabled?"enabled": "disabled");
670 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
671 /* if this is not a multi function device, don't
672 * waste time probe another function.
673 * Skip to next device. */
679 /* if a child provides scan_bus(), for example a bridge, scan
680 * buses behind that child */
681 for (child = bus->children; child; child = child->sibling) {
682 // make sure that we have an ops structure
686 if (!child->ops->scan_bus) {
689 max = child->ops->scan_bus(child, max);
693 * We've scanned the bus and so we know all about what's on
694 * the other side of any bridges that may be on this bus plus
697 * Return how far we've got finding sub-buses.
699 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
705 * @brief Scan a PCI bridge and the buses behind the bridge.
707 * Determine the existence of buses behind the bridge. Set up the bridge
708 * according to the result of the scan.
710 * This function is the default scan_bus() method for PCI bridge devices.
712 * @param dev pointer to the bridge device
713 * @param max the highest bus number assgined up to now
715 * @return The maximum bus number found, after scanning all subordinate busses
717 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
726 /* Set up the primary, secondary and subordinate bus numbers. We have
727 * no idea how many buses are behind this bridge yet, so we set the
728 * subordinate bus number to 0xff for the moment. */
729 bus->secondary = ++max;
730 bus->subordinate = 0xff;
732 /* Clear all status bits and turn off memory, I/O and master enables. */
733 cr = pci_read_config16(dev, PCI_COMMAND);
734 pci_write_config16(dev, PCI_COMMAND, 0x0000);
735 pci_write_config16(dev, PCI_STATUS, 0xffff);
737 /* Read the existing primary/secondary/subordinate bus
738 * number configuration. */
739 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
741 /* Configure the bus numbers for this bridge: the configuration
742 * transactions will not be propagated by the bridge if it is not
743 * correctly configured */
745 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
746 ((unsigned int) (bus->secondary) << 8) |
747 ((unsigned int) (bus->subordinate) << 16));
748 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
750 /* Now we can scan all subordinate buses i.e. the buses behind the
752 max = pci_scan_bus(bus, 0x00, 0xff, max);
754 /* We know the number of buses behind this bridge. Set the subordinate
755 * bus number to its real value */
756 bus->subordinate = max;
757 buses = (buses & 0xff00ffff) |
758 ((unsigned int) (bus->subordinate) << 16);
759 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
760 pci_write_config16(dev, PCI_COMMAND, cr);
762 printk_spew("%s returns max %d\n", __FUNCTION__, max);
767 Tell the EISA int controller this int must be level triggered
768 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
770 static void pci_level_irq(unsigned char intNum)
772 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
774 printk_debug("%s: current ints are 0x%x\n", __FUNCTION__, intBits);
775 intBits |= (1 << intNum);
777 printk_debug("%s: try to set ints 0x%x\n", __FUNCTION__, intBits);
780 outb((unsigned char) intBits, 0x4d0);
781 outb((unsigned char) (intBits >> 8), 0x4d1);
783 /* this seems like an error but is not ... */
785 if (inb(0x4d0) != (intBits & 0xf)) {
786 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
787 __FUNCTION__, intBits &0xf, inb(0x4d0));
789 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
790 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
791 __FUNCTION__, (intBits>>8) &0xf, inb(0x4d1));
797 This function assigns IRQs for all functions contained within
798 the indicated device address. If the device does not exist or does
799 not require interrupts then this function has no effect.
801 This function should be called for each PCI slot in your system.
803 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
805 The particular irq #s that are passed in depend on the routing inside
806 your southbridge and on your motherboard.
810 void pci_assign_irqs(unsigned bus, unsigned slot,
811 const unsigned char pIntAtoD[4])
817 unsigned char readback;
819 /* Each slot may contain up to eight functions */
820 for (functNum = 0; functNum < 8; functNum++) {
821 pdev = dev_find_slot(bus, (slot << 3) + functNum);
824 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
826 // PCI spec says all other values are reserved
827 if ((line >= 1) && (line <= 4)) {
828 irq = pIntAtoD[line - 1];
830 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
831 irq, bus, slot, functNum);
833 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
836 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
837 printk_debug(" Readback = %d\n", readback);
839 // Change to level triggered
840 pci_level_irq(pIntAtoD[line - 1]);