2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
36 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
37 #include <device/hypertransport.h>
39 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
40 #include <device/pcix.h>
42 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
43 #include <device/pciexp.h>
45 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
46 #include <device/agp.h>
48 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
49 #include <device/cardbus.h>
51 #if CONFIG_PC80_SYSTEM == 1
52 #include <pc80/i8259.h>
54 #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
55 #include <arch/acpi.h>
58 #include <vendorcode/google/chromeos/chromeos.h>
61 u8 pci_moving_config8(struct device *dev, unsigned int reg)
63 u8 value, ones, zeroes;
65 value = pci_read_config8(dev, reg);
67 pci_write_config8(dev, reg, 0xff);
68 ones = pci_read_config8(dev, reg);
70 pci_write_config8(dev, reg, 0x00);
71 zeroes = pci_read_config8(dev, reg);
73 pci_write_config8(dev, reg, value);
78 u16 pci_moving_config16(struct device *dev, unsigned int reg)
80 u16 value, ones, zeroes;
82 value = pci_read_config16(dev, reg);
84 pci_write_config16(dev, reg, 0xffff);
85 ones = pci_read_config16(dev, reg);
87 pci_write_config16(dev, reg, 0x0000);
88 zeroes = pci_read_config16(dev, reg);
90 pci_write_config16(dev, reg, value);
95 u32 pci_moving_config32(struct device *dev, unsigned int reg)
97 u32 value, ones, zeroes;
99 value = pci_read_config32(dev, reg);
101 pci_write_config32(dev, reg, 0xffffffff);
102 ones = pci_read_config32(dev, reg);
104 pci_write_config32(dev, reg, 0x00000000);
105 zeroes = pci_read_config32(dev, reg);
107 pci_write_config32(dev, reg, value);
109 return ones ^ zeroes;
113 * Given a device, a capability type, and a last position, return the next
114 * matching capability. Always start at the head of the list.
116 * @param dev Pointer to the device structure.
117 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
118 * @param last Location of the PCI capability register to start from.
119 * @return The next matching capability.
121 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
128 status = pci_read_config16(dev, PCI_STATUS);
129 if (!(status & PCI_STATUS_CAP_LIST))
132 switch (dev->hdr_type & 0x7f) {
133 case PCI_HEADER_TYPE_NORMAL:
134 case PCI_HEADER_TYPE_BRIDGE:
135 pos = PCI_CAPABILITY_LIST;
137 case PCI_HEADER_TYPE_CARDBUS:
138 pos = PCI_CB_CAPABILITY_LIST;
144 pos = pci_read_config8(dev, pos);
145 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
149 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
150 printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n",
152 if (this_cap == 0xff)
155 if (!last && (this_cap == cap))
161 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
167 * Given a device, and a capability type, return the next matching
168 * capability. Always start at the head of the list.
170 * @param dev Pointer to the device structure.
171 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
172 * @return The next matching capability.
174 unsigned pci_find_capability(device_t dev, unsigned cap)
176 return pci_find_next_capability(dev, cap, 0);
180 * Given a device and register, read the size of the BAR for that register.
182 * @param dev Pointer to the device structure.
183 * @param index Address of the PCI configuration register.
186 struct resource *pci_get_resource(struct device *dev, unsigned long index)
188 struct resource *resource;
189 unsigned long value, attr;
190 resource_t moving, limit;
192 /* Initialize the resources to nothing. */
193 resource = new_resource(dev, index);
195 /* Get the initial value. */
196 value = pci_read_config32(dev, index);
198 /* See which bits move. */
199 moving = pci_moving_config32(dev, index);
201 /* Initialize attr to the bits that do not move. */
202 attr = value & ~moving;
204 /* If it is a 64bit resource look at the high half as well. */
205 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
206 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
207 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
208 /* Find the high bits that move. */
210 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
213 /* Find the resource constraints.
214 * Start by finding the bits that move. From there:
215 * - Size is the least significant bit of the bits that move.
216 * - Limit is all of the bits that move plus all of the lower bits.
217 * See PCI Spec 6.2.5.1.
222 resource->align = resource->gran = 0;
223 while (!(moving & resource->size)) {
224 resource->size <<= 1;
225 resource->align += 1;
228 resource->limit = limit = moving | (resource->size - 1);
232 * Some broken hardware has read-only registers that do not
233 * really size correctly.
235 * Example: the Acer M7229 has BARs 1-4 normally read-only,
236 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
237 * by writing 0xffffffff to it, it will read back as 0x1f1 -- which
238 * is a violation of the spec.
240 * We catch this case and ignore it by observing which bits move.
242 * This also catches the common case of unimplemented registers
243 * that always read back as 0.
247 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
248 "read-only ignoring it\n",
249 dev_path(dev), index, value);
252 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
253 /* An I/O mapped base address. */
254 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
255 resource->flags |= IORESOURCE_IO;
256 /* I don't want to deal with 32bit I/O resources. */
257 resource->limit = 0xffff;
259 /* A Memory mapped base address. */
260 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
261 resource->flags |= IORESOURCE_MEM;
262 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
263 resource->flags |= IORESOURCE_PREFETCH;
264 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
265 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
267 resource->limit = 0xffffffffUL;
268 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
270 resource->limit = 0x000fffffUL;
271 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
273 resource->limit = 0xffffffffffffffffULL;
274 resource->flags |= IORESOURCE_PCI64;
277 printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
278 printk(BIOS_ERR, " on dev %s at index %02lx\n",
279 dev_path(dev), index);
284 /* Don't let the limit exceed which bits can move. */
285 if (resource->limit > limit)
286 resource->limit = limit;
292 * Given a device and an index, read the size of the BAR for that register.
294 * @param dev Pointer to the device structure.
295 * @param index Address of the PCI configuration register.
297 static void pci_get_rom_resource(struct device *dev, unsigned long index)
299 struct resource *resource;
303 /* Initialize the resources to nothing. */
304 resource = new_resource(dev, index);
306 /* Get the initial value. */
307 value = pci_read_config32(dev, index);
309 /* See which bits move. */
310 moving = pci_moving_config32(dev, index);
312 /* Clear the Enable bit. */
313 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
315 /* Find the resource constraints.
316 * Start by finding the bits that move. From there:
317 * - Size is the least significant bit of the bits that move.
318 * - Limit is all of the bits that move plus all of the lower bits.
319 * See PCI Spec 6.2.5.1.
323 resource->align = resource->gran = 0;
324 while (!(moving & resource->size)) {
325 resource->size <<= 1;
326 resource->align += 1;
329 resource->limit = moving | (resource->size - 1);
330 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
333 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
334 "read-only ignoring it\n",
335 dev_path(dev), index, value);
339 compact_resources(dev);
343 * Read the base address registers for a given device.
345 * @param dev Pointer to the dev structure.
346 * @param howmany How many registers to read (6 for device, 2 for bridge).
348 static void pci_read_bases(struct device *dev, unsigned int howmany)
352 for (index = PCI_BASE_ADDRESS_0;
353 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
354 struct resource *resource;
355 resource = pci_get_resource(dev, index);
356 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
359 compact_resources(dev);
362 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
363 unsigned index, unsigned long type)
365 struct resource *resource;
374 /* Initialize the constraints on the current bus. */
375 resource = new_resource(dev, index);
379 while ((moving & step) == 0) {
383 resource->gran = gran;
384 resource->align = gran;
385 resource->limit = moving | (step - 1);
386 resource->flags = type | IORESOURCE_PCI_BRIDGE |
390 static void pci_bridge_read_bases(struct device *dev)
392 resource_t moving_base, moving_limit, moving;
394 /* See if the bridge I/O resources are implemented. */
395 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
397 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
399 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
401 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
403 moving = moving_base & moving_limit;
405 /* Initialize the I/O space constraints on the current bus. */
406 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
408 /* See if the bridge prefmem resources are implemented. */
410 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
412 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
415 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
417 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
419 moving = moving_base & moving_limit;
420 /* Initialize the prefetchable memory constraints on the current bus. */
421 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
422 IORESOURCE_MEM | IORESOURCE_PREFETCH);
424 /* See if the bridge mem resources are implemented. */
425 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
426 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
428 moving = moving_base & moving_limit;
430 /* Initialize the memory resources on the current bus. */
431 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
434 compact_resources(dev);
437 void pci_dev_read_resources(struct device *dev)
439 pci_read_bases(dev, 6);
440 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
443 void pci_bus_read_resources(struct device *dev)
445 pci_bridge_read_bases(dev);
446 pci_read_bases(dev, 2);
447 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
450 void pci_domain_read_resources(struct device *dev)
452 struct resource *res;
454 /* Initialize the system-wide I/O space constraints. */
455 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
456 res->limit = 0xffffUL;
457 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
460 /* Initialize the system-wide memory resources constraints. */
461 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
462 res->limit = 0xffffffffULL;
463 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
467 static void pci_set_resource(struct device *dev, struct resource *resource)
469 resource_t base, end;
471 /* Make certain the resource has actually been assigned a value. */
472 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
473 printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
474 "assigned\n", dev_path(dev), resource->index,
475 resource_type(resource), resource->size);
479 /* If this resource is fixed don't worry about it. */
480 if (resource->flags & IORESOURCE_FIXED)
483 /* If I have already stored this resource don't worry about it. */
484 if (resource->flags & IORESOURCE_STORED)
487 /* If the resource is subtractive don't worry about it. */
488 if (resource->flags & IORESOURCE_SUBTRACTIVE)
491 /* Only handle PCI memory and I/O resources for now. */
492 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
495 /* Enable the resources in the command register. */
496 if (resource->size) {
497 if (resource->flags & IORESOURCE_MEM)
498 dev->command |= PCI_COMMAND_MEMORY;
499 if (resource->flags & IORESOURCE_IO)
500 dev->command |= PCI_COMMAND_IO;
501 if (resource->flags & IORESOURCE_PCI_BRIDGE)
502 dev->command |= PCI_COMMAND_MASTER;
505 /* Get the base address. */
506 base = resource->base;
509 end = resource_end(resource);
511 /* Now store the resource. */
512 resource->flags |= IORESOURCE_STORED;
515 * PCI bridges have no enable bit. They are disabled if the base of
516 * the range is greater than the limit. If the size is zero, disable
517 * by setting the base = limit and end = limit - 2^gran.
519 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
520 base = resource->limit;
521 end = resource->limit - (1 << resource->gran);
522 resource->base = base;
525 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
526 unsigned long base_lo, base_hi;
529 * Some chipsets allow us to set/clear the I/O bit
530 * (e.g. VIA 82C686A). So set it to be safe.
532 base_lo = base & 0xffffffff;
533 base_hi = (base >> 32) & 0xffffffff;
534 if (resource->flags & IORESOURCE_IO)
535 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
536 pci_write_config32(dev, resource->index, base_lo);
537 if (resource->flags & IORESOURCE_PCI64)
538 pci_write_config32(dev, resource->index + 4, base_hi);
539 } else if (resource->index == PCI_IO_BASE) {
540 /* Set the I/O ranges. */
541 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
542 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
543 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
544 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
545 } else if (resource->index == PCI_MEMORY_BASE) {
546 /* Set the memory range. */
547 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
548 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
549 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
550 /* Set the prefetchable memory range. */
551 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
552 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
553 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
554 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
556 /* Don't let me think I stored the resource. */
557 resource->flags &= ~IORESOURCE_STORED;
558 printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
562 report_resource_stored(dev, resource, "");
565 void pci_dev_set_resources(struct device *dev)
567 struct resource *res;
571 for (res = dev->resource_list; res; res = res->next)
572 pci_set_resource(dev, res);
574 for (bus = dev->link_list; bus; bus = bus->next) {
576 assign_resources(bus);
579 /* Set a default latency timer. */
580 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
582 /* Set a default secondary latency timer. */
583 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
584 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
586 /* Zero the IRQ settings. */
587 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
589 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
591 /* Set the cache line size, so far 64 bytes is good for everyone. */
592 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
595 void pci_dev_enable_resources(struct device *dev)
597 const struct pci_operations *ops;
600 /* Set the subsystem vendor and device ID for mainboard devices. */
602 if (dev->on_mainboard && ops && ops->set_subsystem) {
603 printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
604 dev_path(dev), dev->subsystem_vendor,
605 dev->subsystem_device);
606 ops->set_subsystem(dev, dev->subsystem_vendor,
607 dev->subsystem_device);
609 command = pci_read_config16(dev, PCI_COMMAND);
610 command |= dev->command;
613 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
616 printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
617 pci_write_config16(dev, PCI_COMMAND, command);
620 void pci_bus_enable_resources(struct device *dev)
625 * Enable I/O in command register if there is VGA card
626 * connected with (even it does not claim I/O resource).
628 if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
629 dev->command |= PCI_COMMAND_IO;
630 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
631 ctrl |= dev->link_list->bridge_ctrl;
632 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
633 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
634 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
636 pci_dev_enable_resources(dev);
639 void pci_bus_reset(struct bus *bus)
643 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
644 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
645 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
648 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
649 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
653 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
655 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
656 ((device & 0xffff) << 16) | (vendor & 0xffff));
659 /** Default handler: only runs the relevant PCI BIOS. */
660 void pci_dev_init(struct device *dev)
662 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
663 struct rom_header *rom, *ram;
665 if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
666 ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
669 if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
670 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
674 /* In ChromeOS we want to boot blazingly fast. Therefore
675 * we don't run (VGA) option ROMs, unless we have to print
676 * something on the screen before the kernel is loaded.
678 if (!developer_mode_enabled() && !recovery_mode_enabled())
682 rom = pci_rom_probe(dev);
686 ram = pci_rom_load(dev, rom);
690 #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
691 /* If S3_VGA_ROM_RUN is disabled, skip running VGA option
692 * ROMs when coming out of an S3 resume.
694 if ((acpi_slp_type == 3) &&
695 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
698 run_bios(dev, (unsigned long)ram);
699 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
702 /** Default device operation for PCI devices */
703 static struct pci_operations pci_dev_ops_pci = {
704 .set_subsystem = pci_dev_set_subsystem,
707 struct device_operations default_pci_ops_dev = {
708 .read_resources = pci_dev_read_resources,
709 .set_resources = pci_dev_set_resources,
710 .enable_resources = pci_dev_enable_resources,
711 .init = pci_dev_init,
714 .ops_pci = &pci_dev_ops_pci,
717 /** Default device operations for PCI bridges */
718 static struct pci_operations pci_bus_ops_pci = {
722 struct device_operations default_pci_ops_bus = {
723 .read_resources = pci_bus_read_resources,
724 .set_resources = pci_dev_set_resources,
725 .enable_resources = pci_bus_enable_resources,
727 .scan_bus = pci_scan_bridge,
729 .reset_bus = pci_bus_reset,
730 .ops_pci = &pci_bus_ops_pci,
734 * Detect the type of downstream bridge.
736 * This function is a heuristic to detect which type of bus is downstream
737 * of a PCI-to-PCI bridge. This functions by looking for various capability
738 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
739 * Hypertransport all seem to have appropriate capabilities.
741 * When only a PCI-Express capability is found the type is examined to see
742 * which type of bridge we have.
744 * @param dev Pointer to the device structure of the bridge.
745 * @return Appropriate bridge operations.
747 static struct device_operations *get_pci_bridge_ops(device_t dev)
751 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
752 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
754 printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
755 return &default_pcix_ops_bus;
758 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
759 /* How do I detect a PCI to AGP bridge? */
761 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
763 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
765 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
766 if ((flags >> 13) == 1) {
767 /* Host or Secondary Interface */
768 printk(BIOS_DEBUG, "%s subordinate bus HT\n",
770 return &default_ht_ops_bus;
774 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
775 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
778 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
779 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
780 case PCI_EXP_TYPE_ROOT_PORT:
781 case PCI_EXP_TYPE_UPSTREAM:
782 case PCI_EXP_TYPE_DOWNSTREAM:
783 printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
785 return &default_pciexp_ops_bus;
786 case PCI_EXP_TYPE_PCI_BRIDGE:
787 printk(BIOS_DEBUG, "%s subordinate PCI\n",
789 return &default_pci_ops_bus;
795 return &default_pci_ops_bus;
799 * Set up PCI device operation.
801 * Check if it already has a driver. If not, use find_device_operations(),
802 * or set to a default based on type.
804 * @param dev Pointer to the device whose pci_ops you want to set.
807 static void set_pci_ops(struct device *dev)
809 struct pci_driver *driver;
815 * Look through the list of setup drivers and find one for
818 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
819 if ((driver->vendor == dev->vendor) &&
820 (driver->device == dev->device)) {
821 dev->ops = (struct device_operations *)driver->ops;
822 printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
823 dev_path(dev), driver->vendor, driver->device,
824 (driver->ops->scan_bus ? "bus " : ""));
829 /* If I don't have a specific driver use the default operations. */
830 switch (dev->hdr_type & 0x7f) { /* Header type */
831 case PCI_HEADER_TYPE_NORMAL:
832 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
834 dev->ops = &default_pci_ops_dev;
836 case PCI_HEADER_TYPE_BRIDGE:
837 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
839 dev->ops = get_pci_bridge_ops(dev);
841 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
842 case PCI_HEADER_TYPE_CARDBUS:
843 dev->ops = &default_cardbus_ops_bus;
849 printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
850 "header type %02x, ignoring.\n", dev_path(dev),
851 dev->vendor, dev->device,
852 dev->class >> 8, dev->hdr_type);
858 * See if we have already allocated a device structure for a given devfn.
860 * Given a linked list of PCI device structures and a devfn number, find the
861 * device structure correspond to the devfn, if present. This function also
862 * removes the device structure from the linked list.
864 * @param list The device structure list.
865 * @param devfn A device/function number.
866 * @return Pointer to the device structure found or NULL if we have not
867 * allocated a device for this devfn yet.
869 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
874 for (; *list; list = &(*list)->sibling) {
875 if ((*list)->path.type != DEVICE_PATH_PCI) {
876 printk(BIOS_ERR, "child %s not a PCI device\n",
880 if ((*list)->path.pci.devfn == devfn) {
881 /* Unlink from the list. */
883 *list = (*list)->sibling;
890 * Just like alloc_dev() add the device to the list of devices on the
891 * bus. When the list of devices was formed we removed all of the
892 * parents children, and now we are interleaving static and dynamic
893 * devices in order on the bus.
896 struct device *child;
898 /* Find the last child of our parent. */
899 for (child = dev->bus->children; child && child->sibling;)
900 child = child->sibling;
902 /* Place the device on the list of children of its parent. */
904 child->sibling = dev;
906 dev->bus->children = dev;
915 * Determine the existence of a given PCI device. Allocate a new struct device
916 * if dev==NULL was passed in and the device exists in hardware.
918 * @param dev Pointer to the dev structure.
919 * @param bus Pointer to the bus structure.
920 * @param devfn A device/function number to look at.
921 * @return The device structure for the device (if found), NULL otherwise.
923 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
928 /* Detect if a device is present. */
933 dummy.path.type = DEVICE_PATH_PCI;
934 dummy.path.pci.devfn = devfn;
936 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
938 * Have we found something? Some broken boards return 0 if a
939 * slot is empty, but the expected answer is 0xffffffff.
941 if (id == 0xffffffff)
944 if ((id == 0x00000000) || (id == 0x0000ffff) ||
945 (id == 0xffff0000)) {
946 printk(BIOS_SPEW, "%s, bad id 0x%x\n",
947 dev_path(&dummy), id);
950 dev = alloc_dev(bus, &dummy.path);
953 * Enable/disable the device. Once we have found the device-
954 * specific operations this operations we will disable the
955 * device with those as well.
957 * This is geared toward devices that have subfunctions
958 * that do not show up by default.
960 * If a device is a stuff option on the motherboard
961 * it may be absent and enable_dev() must cope.
963 /* Run the magic enable sequence for the device. */
964 if (dev->chip_ops && dev->chip_ops->enable_dev)
965 dev->chip_ops->enable_dev(dev);
967 /* Now read the vendor and device ID. */
968 id = pci_read_config32(dev, PCI_VENDOR_ID);
971 * If the device does not have a PCI ID disable it. Possibly
972 * this is because we have already disabled the device. But
973 * this also handles optional devices that may not always
976 /* If the chain is fully enumerated quit */
977 if ((id == 0xffffffff) || (id == 0x00000000) ||
978 (id == 0x0000ffff) || (id == 0xffff0000)) {
980 printk(BIOS_INFO, "PCI: Static device %s not "
981 "found, disabling it.\n", dev_path(dev));
988 /* Read the rest of the PCI configuration information. */
989 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
990 class = pci_read_config32(dev, PCI_CLASS_REVISION);
992 /* Store the interesting information in the device structure. */
993 dev->vendor = id & 0xffff;
994 dev->device = (id >> 16) & 0xffff;
995 dev->hdr_type = hdr_type;
997 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
998 dev->class = class >> 8;
1000 /* Architectural/System devices always need to be bus masters. */
1001 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
1002 dev->command |= PCI_COMMAND_MASTER;
1005 * Look at the vendor and device ID, or at least the header type and
1006 * class and figure out which set of configuration methods to use.
1007 * Unless we already have some PCI ops.
1011 /* Now run the magic enable/disable sequence for the device. */
1012 if (dev->ops && dev->ops->enable)
1013 dev->ops->enable(dev);
1015 /* Display the device. */
1016 printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev),
1017 dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled",
1018 dev->ops ? "" : " No operations");
1026 * Determine the existence of devices and bridges on a PCI bus. If there are
1027 * bridges on the bus, recursively scan the buses behind the bridges.
1029 * This function is the default scan_bus() method for the root device
1032 * @param bus Pointer to the bus structure.
1033 * @param min_devfn Minimum devfn to look at in the scan, usually 0x00.
1034 * @param max_devfn Maximum devfn to look at in the scan, usually 0xff.
1035 * @param max Current bus number.
1036 * @return The maximum bus number found, after scanning all subordinate busses.
1038 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
1039 unsigned max_devfn, unsigned int max)
1042 struct device *old_devices;
1043 struct device *child;
1045 #if CONFIG_PCI_BUS_SEGN_BITS
1046 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
1047 bus->secondary >> 8, bus->secondary & 0xff);
1049 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1052 /* Maximum sane devfn is 0xFF. */
1053 if (max_devfn > 0xff) {
1054 printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
1055 "devfn %x\n", min_devfn, max_devfn);
1056 printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
1061 old_devices = bus->children;
1062 bus->children = NULL;
1067 * Probe all devices/functions on this bus with some optimization for
1068 * non-existence and single function devices.
1070 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1073 /* First thing setup the device structure. */
1074 dev = pci_scan_get_dev(&old_devices, devfn);
1076 /* See if a device is present and setup the device structure. */
1077 dev = pci_probe_dev(dev, bus, devfn);
1080 * If this is not a multi function device, or the device is
1081 * not present don't waste time probing another function.
1082 * Skip to next device.
1084 if ((PCI_FUNC(devfn) == 0x00) && (!dev
1085 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1093 * Warn if any leftover static devices are are found.
1094 * There's probably a problem in devicetree.cb.
1098 printk(BIOS_WARNING, "PCI: Left over static devices:\n");
1099 for (left = old_devices; left; left = left->sibling)
1100 printk(BIOS_WARNING, "%s\n", dev_path(left));
1102 printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n");
1106 * For all children that implement scan_bus() (i.e. bridges)
1107 * scan the bus behind that child.
1109 for (child = bus->children; child; child = child->sibling)
1110 max = scan_bus(child, max);
1113 * We've scanned the bus and so we know all about what's on the other
1114 * side of any bridges that may be on this bus plus any devices.
1115 * Return how far we've got finding sub-buses.
1117 printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
1123 * Scan a PCI bridge and the buses behind the bridge.
1125 * Determine the existence of buses behind the bridge. Set up the bridge
1126 * according to the result of the scan.
1128 * This function is the default scan_bus() method for PCI bridge devices.
1130 * @param dev Pointer to the bridge device.
1131 * @param max The highest bus number assigned up to now.
1132 * @param do_scan_bus TODO
1133 * @return The maximum bus number found, after scanning all subordinate buses.
1135 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1136 unsigned int (*do_scan_bus) (struct bus * bus,
1145 printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
1147 if (dev->link_list == NULL) {
1149 link = malloc(sizeof(*link));
1151 die("Couldn't allocate a link!\n");
1152 memset(link, 0, sizeof(*link));
1154 dev->link_list = link;
1157 bus = dev->link_list;
1160 * Set up the primary, secondary and subordinate bus numbers. We have
1161 * no idea how many buses are behind this bridge yet, so we set the
1162 * subordinate bus number to 0xff for the moment.
1164 bus->secondary = ++max;
1165 bus->subordinate = 0xff;
1167 /* Clear all status bits and turn off memory, I/O and master enables. */
1168 cr = pci_read_config16(dev, PCI_COMMAND);
1169 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1170 pci_write_config16(dev, PCI_STATUS, 0xffff);
1173 * Read the existing primary/secondary/subordinate bus
1174 * number configuration.
1176 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1179 * Configure the bus numbers for this bridge: the configuration
1180 * transactions will not be propagated by the bridge if it is not
1181 * correctly configured.
1183 buses &= 0xff000000;
1184 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1185 ((unsigned int)(bus->secondary) << 8) |
1186 ((unsigned int)(bus->subordinate) << 16));
1187 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1189 /* Now we can scan all subordinate buses (those behind the bridge). */
1190 max = do_scan_bus(bus, 0x00, 0xff, max);
1193 * We know the number of buses behind this bridge. Set the subordinate
1194 * bus number to its real value.
1196 bus->subordinate = max;
1197 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1198 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1199 pci_write_config16(dev, PCI_COMMAND, cr);
1201 printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
1206 * Scan a PCI bridge and the buses behind the bridge.
1208 * Determine the existence of buses behind the bridge. Set up the bridge
1209 * according to the result of the scan.
1211 * This function is the default scan_bus() method for PCI bridge devices.
1213 * @param dev Pointer to the bridge device.
1214 * @param max The highest bus number assigned up to now.
1215 * @return The maximum bus number found, after scanning all subordinate buses.
1217 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1219 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1223 * Scan a PCI domain.
1225 * This function is the default scan_bus() method for PCI domains.
1227 * @param dev Pointer to the domain.
1228 * @param max The highest bus number assigned up to now.
1229 * @return The maximum bus number found, after scanning all subordinate busses.
1231 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1233 max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
1237 #if CONFIG_PC80_SYSTEM == 1
1239 * Assign IRQ numbers.
1241 * This function assigns IRQs for all functions contained within the indicated
1242 * device address. If the device does not exist or does not require interrupts
1243 * then this function has no effect.
1245 * This function should be called for each PCI slot in your system.
1247 * @param bus Pointer to the bus structure.
1249 * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD
1250 * of this slot. The particular IRQ #s that are passed in depend on the
1251 * routing inside your southbridge and on your board.
1253 void pci_assign_irqs(unsigned bus, unsigned slot,
1254 const unsigned char pIntAtoD[4])
1260 /* Each slot may contain up to eight functions. */
1261 for (funct = 0; funct < 8; funct++) {
1262 pdev = dev_find_slot(bus, (slot << 3) + funct);
1267 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1269 /* PCI spec says all values except 1..4 are reserved. */
1270 if ((line < 1) || (line > 4))
1273 irq = pIntAtoD[line - 1];
1275 printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
1276 irq, bus, slot, funct);
1278 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1279 pIntAtoD[line - 1]);
1281 #ifdef PARANOID_IRQ_ASSIGNMENTS
1282 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1283 printk(BIOS_DEBUG, " Readback = %d\n", irq);
1286 #if CONFIG_PC80_SYSTEM == 1
1287 /* Change to level triggered. */
1288 i8259_configure_irq_trigger(pIntAtoD[line - 1],
1289 IRQ_LEVEL_TRIGGERED);