2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
36 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
37 #include <device/hypertransport.h>
39 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
40 #include <device/pcix.h>
42 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
43 #include <device/pciexp.h>
45 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
46 #include <device/agp.h>
48 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
49 #include <device/cardbus.h>
51 #define CONFIG_PC80_SYSTEM 1
52 #if CONFIG_PC80_SYSTEM == 1
53 #include <pc80/i8259.h>
56 u8 pci_moving_config8(struct device *dev, unsigned int reg)
58 u8 value, ones, zeroes;
59 value = pci_read_config8(dev, reg);
61 pci_write_config8(dev, reg, 0xff);
62 ones = pci_read_config8(dev, reg);
64 pci_write_config8(dev, reg, 0x00);
65 zeroes = pci_read_config8(dev, reg);
67 pci_write_config8(dev, reg, value);
72 u16 pci_moving_config16(struct device * dev, unsigned int reg)
74 u16 value, ones, zeroes;
75 value = pci_read_config16(dev, reg);
77 pci_write_config16(dev, reg, 0xffff);
78 ones = pci_read_config16(dev, reg);
80 pci_write_config16(dev, reg, 0x0000);
81 zeroes = pci_read_config16(dev, reg);
83 pci_write_config16(dev, reg, value);
88 u32 pci_moving_config32(struct device * dev, unsigned int reg)
90 u32 value, ones, zeroes;
91 value = pci_read_config32(dev, reg);
93 pci_write_config32(dev, reg, 0xffffffff);
94 ones = pci_read_config32(dev, reg);
96 pci_write_config32(dev, reg, 0x00000000);
97 zeroes = pci_read_config32(dev, reg);
99 pci_write_config32(dev, reg, value);
101 return ones ^ zeroes;
105 * Given a device, a capability type, and a last position, return the next
106 * matching capability. Always start at the head of the list.
108 * @param dev Pointer to the device structure.
109 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
110 * @param last Location of the PCI capability register to start from.
112 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
119 status = pci_read_config16(dev, PCI_STATUS);
120 if (!(status & PCI_STATUS_CAP_LIST)) {
123 switch (dev->hdr_type & 0x7f) {
124 case PCI_HEADER_TYPE_NORMAL:
125 case PCI_HEADER_TYPE_BRIDGE:
126 pos = PCI_CAPABILITY_LIST;
128 case PCI_HEADER_TYPE_CARDBUS:
129 pos = PCI_CB_CAPABILITY_LIST;
134 pos = pci_read_config8(dev, pos);
135 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
138 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
139 printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", this_cap,
141 if (this_cap == 0xff) {
144 if (!last && (this_cap == cap)) {
150 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
156 * Given a device, and a capability type, return the next matching
157 * capability. Always start at the head of the list.
159 * @param dev Pointer to the device structure.
160 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
162 unsigned pci_find_capability(device_t dev, unsigned cap)
164 return pci_find_next_capability(dev, cap, 0);
168 * Given a device and register, read the size of the BAR for that register.
170 * @param dev Pointer to the device structure.
171 * @param index Address of the PCI configuration register.
173 struct resource *pci_get_resource(struct device *dev, unsigned long index)
175 struct resource *resource;
176 unsigned long value, attr;
177 resource_t moving, limit;
179 /* Initialize the resources to nothing. */
180 resource = new_resource(dev, index);
182 /* Get the initial value. */
183 value = pci_read_config32(dev, index);
185 /* See which bits move. */
186 moving = pci_moving_config32(dev, index);
188 /* Initialize attr to the bits that do not move. */
189 attr = value & ~moving;
191 /* If it is a 64bit resource look at the high half as well. */
192 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
193 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
194 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
195 /* Find the high bits that move. */
197 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
199 /* Find the resource constraints.
200 * Start by finding the bits that move. From there:
201 * - Size is the least significant bit of the bits that move.
202 * - Limit is all of the bits that move plus all of the lower bits.
203 * See PCI Spec 6.2.5.1.
208 resource->align = resource->gran = 0;
209 while (!(moving & resource->size)) {
210 resource->size <<= 1;
211 resource->align += 1;
214 resource->limit = limit = moving | (resource->size - 1);
217 /* Some broken hardware has read-only registers that do not
218 * really size correctly.
219 * Example: the Acer M7229 has BARs 1-4 normally read-only.
220 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
221 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
222 * violation of the spec.
223 * We catch this case and ignore it by observing which bits move,
224 * This also catches the common case unimplemented registers
225 * that always read back as 0.
229 printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
230 dev_path(dev), index, value);
233 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
234 /* An I/O mapped base address. */
235 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
236 resource->flags |= IORESOURCE_IO;
237 /* I don't want to deal with 32bit I/O resources. */
238 resource->limit = 0xffff;
240 /* A Memory mapped base address. */
241 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
242 resource->flags |= IORESOURCE_MEM;
243 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
244 resource->flags |= IORESOURCE_PREFETCH;
246 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
247 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
249 resource->limit = 0xffffffffUL;
250 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
252 resource->limit = 0x000fffffUL;
253 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
255 resource->limit = 0xffffffffffffffffULL;
256 resource->flags |= IORESOURCE_PCI64;
259 printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
260 printk(BIOS_ERR, " on dev %s at index %02lx\n",
261 dev_path(dev), index);
265 /* Don't let the limit exceed which bits can move. */
266 if (resource->limit > limit) {
267 resource->limit = limit;
274 * Given a device and an index, read the size of the BAR for that register.
276 * @param dev Pointer to the device structure.
277 * @param index Address of the PCI configuration register.
279 static void pci_get_rom_resource(struct device *dev, unsigned long index)
281 struct resource *resource;
285 /* Initialize the resources to nothing. */
286 resource = new_resource(dev, index);
288 /* Get the initial value. */
289 value = pci_read_config32(dev, index);
291 /* See which bits move. */
292 moving = pci_moving_config32(dev, index);
294 /* Clear the Enable bit. */
295 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
297 /* Find the resource constraints.
298 * Start by finding the bits that move. From there:
299 * - Size is the least significant bit of the bits that move.
300 * - Limit is all of the bits that move plus all of the lower bits.
301 * See PCI Spec 6.2.5.1.
305 resource->align = resource->gran = 0;
306 while (!(moving & resource->size)) {
307 resource->size <<= 1;
308 resource->align += 1;
311 resource->limit = moving | (resource->size - 1);
312 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
315 printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
316 dev_path(dev), index, value);
320 compact_resources(dev);
324 * Read the base address registers for a given device.
326 * @param dev Pointer to the dev structure.
327 * @param howmany How many registers to read (6 for device, 2 for bridge).
329 static void pci_read_bases(struct device *dev, unsigned int howmany)
333 for (index = PCI_BASE_ADDRESS_0;
334 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
335 struct resource *resource;
336 resource = pci_get_resource(dev, index);
337 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
340 compact_resources(dev);
343 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
344 unsigned index, unsigned long type)
346 /* Initialize the constraints on the current bus. */
347 struct resource *resource;
352 resource = new_resource(dev, index);
356 while ((moving & step) == 0) {
360 resource->gran = gran;
361 resource->align = gran;
362 resource->limit = moving | (step - 1);
363 resource->flags = type | IORESOURCE_PCI_BRIDGE |
369 static void pci_bridge_read_bases(struct device *dev)
371 resource_t moving_base, moving_limit, moving;
373 /* See if the bridge I/O resources are implemented. */
374 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
376 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
378 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
380 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
382 moving = moving_base & moving_limit;
384 /* Initialize the I/O space constraints on the current bus. */
385 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
387 /* See if the bridge prefmem resources are implemented. */
389 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
391 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) <<
395 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) <<
398 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) <<
401 moving = moving_base & moving_limit;
402 /* Initialize the prefetchable memory constraints on the current bus. */
403 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
404 IORESOURCE_MEM | IORESOURCE_PREFETCH);
406 /* See if the bridge mem resources are implemented. */
407 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
408 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
410 moving = moving_base & moving_limit;
412 /* Initialize the memory resources on the current bus. */
413 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
416 compact_resources(dev);
419 void pci_dev_read_resources(struct device *dev)
421 pci_read_bases(dev, 6);
422 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
425 void pci_bus_read_resources(struct device *dev)
427 pci_bridge_read_bases(dev);
428 pci_read_bases(dev, 2);
429 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
432 void pci_domain_read_resources(struct device *dev)
434 struct resource *res;
436 /* Initialize the system-wide I/O space constraints. */
437 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
438 res->limit = 0xffffUL;
439 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
442 /* Initialize the system-wide memory resources constraints. */
443 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
444 res->limit = 0xffffffffULL;
445 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
449 static void pci_set_resource(struct device *dev, struct resource *resource)
451 resource_t base, end;
453 /* Make certain the resource has actually been assigned a value. */
454 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
455 printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
456 dev_path(dev), resource->index,
457 resource_type(resource), resource->size);
461 /* If this resource is fixed don't worry about it. */
462 if (resource->flags & IORESOURCE_FIXED) {
466 /* If I have already stored this resource don't worry about it. */
467 if (resource->flags & IORESOURCE_STORED) {
471 /* If the resource is subtractive don't worry about it. */
472 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
476 /* Only handle PCI memory and I/O resources for now. */
477 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
480 /* Enable the resources in the command register. */
481 if (resource->size) {
482 if (resource->flags & IORESOURCE_MEM) {
483 dev->command |= PCI_COMMAND_MEMORY;
485 if (resource->flags & IORESOURCE_IO) {
486 dev->command |= PCI_COMMAND_IO;
488 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
489 dev->command |= PCI_COMMAND_MASTER;
492 /* Get the base address. */
493 base = resource->base;
496 end = resource_end(resource);
498 /* Now store the resource. */
499 resource->flags |= IORESOURCE_STORED;
501 /* PCI Bridges have no enable bit. They are disabled if the base of
502 * the range is greater than the limit. If the size is zero, disable
503 * by setting the base = limit and end = limit - 2^gran.
505 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
506 base = resource->limit;
507 end = resource->limit - (1 << resource->gran);
508 resource->base = base;
511 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
512 unsigned long base_lo, base_hi;
513 /* Some chipsets allow us to set/clear the I/O bit
514 * (e.g. VIA 82c686a). So set it to be safe.
516 base_lo = base & 0xffffffff;
517 base_hi = (base >> 32) & 0xffffffff;
518 if (resource->flags & IORESOURCE_IO) {
519 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
521 pci_write_config32(dev, resource->index, base_lo);
522 if (resource->flags & IORESOURCE_PCI64) {
523 pci_write_config32(dev, resource->index + 4, base_hi);
525 } else if (resource->index == PCI_IO_BASE) {
526 /* Set the I/O ranges. */
527 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
528 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
529 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
530 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
531 } else if (resource->index == PCI_MEMORY_BASE) {
532 /* Set the memory range. */
533 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
534 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
535 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
536 /* Set the prefetchable memory range. */
537 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
538 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
539 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
540 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
542 /* Don't let me think I stored the resource. */
543 resource->flags &= ~IORESOURCE_STORED;
544 printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
547 report_resource_stored(dev, resource, "");
551 void pci_dev_set_resources(struct device *dev)
553 struct resource *resource, *last;
557 last = &dev->resource[dev->resources];
559 for (resource = &dev->resource[0]; resource < last; resource++) {
560 pci_set_resource(dev, resource);
562 for (link = 0; link < dev->links; link++) {
564 bus = &dev->link[link];
566 assign_resources(bus);
570 /* Set a default latency timer. */
571 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
573 /* Set a default secondary latency timer. */
574 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
575 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
578 /* Zero the IRQ settings. */
579 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
581 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
583 /* Set the cache line size, so far 64 bytes is good for everyone. */
584 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
587 void pci_dev_enable_resources(struct device *dev)
589 const struct pci_operations *ops;
592 /* Set the subsystem vendor and device id for mainboard devices. */
594 if (dev->on_mainboard && ops && ops->set_subsystem) {
595 printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
597 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
598 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
599 ops->set_subsystem(dev,
600 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
601 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
603 command = pci_read_config16(dev, PCI_COMMAND);
604 command |= dev->command;
606 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
608 printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
609 pci_write_config16(dev, PCI_COMMAND, command);
612 void pci_bus_enable_resources(struct device *dev)
616 /* Enable I/O in command register if there is VGA card
617 * connected with (even it does not claim I/O resource).
619 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
620 dev->command |= PCI_COMMAND_IO;
621 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
622 ctrl |= dev->link[0].bridge_ctrl;
623 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
624 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
625 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
627 pci_dev_enable_resources(dev);
628 enable_childrens_resources(dev);
631 void pci_bus_reset(struct bus *bus)
634 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
635 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
636 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
638 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
639 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
643 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
645 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
646 ((device & 0xffff) << 16) | (vendor & 0xffff));
649 /** default handler: only runs the relevant pci bios. */
650 void pci_dev_init(struct device *dev)
652 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
653 struct rom_header *rom, *ram;
655 if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
656 ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
659 if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
660 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
663 rom = pci_rom_probe(dev);
667 ram = pci_rom_load(dev, rom);
671 run_bios(dev, (unsigned long)ram);
673 #if CONFIG_CONSOLE_VGA == 1
674 if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA)
676 #endif /* CONFIG_CONSOLE_VGA */
677 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
680 /** Default device operation for PCI devices */
681 static struct pci_operations pci_dev_ops_pci = {
682 .set_subsystem = pci_dev_set_subsystem,
685 struct device_operations default_pci_ops_dev = {
686 .read_resources = pci_dev_read_resources,
687 .set_resources = pci_dev_set_resources,
688 .enable_resources = pci_dev_enable_resources,
689 .init = pci_dev_init,
692 .ops_pci = &pci_dev_ops_pci,
695 /** Default device operations for PCI bridges */
696 static struct pci_operations pci_bus_ops_pci = {
700 struct device_operations default_pci_ops_bus = {
701 .read_resources = pci_bus_read_resources,
702 .set_resources = pci_dev_set_resources,
703 .enable_resources = pci_bus_enable_resources,
705 .scan_bus = pci_scan_bridge,
707 .reset_bus = pci_bus_reset,
708 .ops_pci = &pci_bus_ops_pci,
712 * @brief Detect the type of downstream bridge
714 * This function is a heuristic to detect which type of bus is downstream
715 * of a PCI-to-PCI bridge. This functions by looking for various capability
716 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
717 * Hypertransport all seem to have appropriate capabilities.
719 * When only a PCI-Express capability is found the type
720 * is examined to see which type of bridge we have.
722 * @param dev Pointer to the device structure of the bridge.
723 * @return Appropriate bridge operations.
725 static struct device_operations *get_pci_bridge_ops(device_t dev)
729 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
730 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
732 printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
733 return &default_pcix_ops_bus;
736 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
737 /* How do I detect an PCI to AGP bridge? */
739 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
741 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
743 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
744 if ((flags >> 13) == 1) {
745 /* Host or Secondary Interface */
746 printk(BIOS_DEBUG, "%s subordinate bus Hypertransport\n",
748 return &default_ht_ops_bus;
752 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
753 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
756 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
757 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
758 case PCI_EXP_TYPE_ROOT_PORT:
759 case PCI_EXP_TYPE_UPSTREAM:
760 case PCI_EXP_TYPE_DOWNSTREAM:
761 printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
763 return &default_pciexp_ops_bus;
764 case PCI_EXP_TYPE_PCI_BRIDGE:
765 printk(BIOS_DEBUG, "%s subordinate PCI\n", dev_path(dev));
766 return &default_pci_ops_bus;
772 return &default_pci_ops_bus;
776 * Set up PCI device operation. Check if it already has a driver. If not, use
777 * find_device_operations, or set to a default based on type.
779 * @param dev Pointer to the device whose pci_ops you want to set.
782 static void set_pci_ops(struct device *dev)
784 struct pci_driver *driver;
789 /* Look through the list of setup drivers and find one for
792 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
793 if ((driver->vendor == dev->vendor) &&
794 (driver->device == dev->device)) {
795 dev->ops = (struct device_operations *)driver->ops;
796 printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
798 driver->vendor, driver->device,
799 (driver->ops->scan_bus ? "bus " : ""));
804 /* If I don't have a specific driver use the default operations */
805 switch (dev->hdr_type & 0x7f) { /* header type */
806 case PCI_HEADER_TYPE_NORMAL: /* standard header */
807 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
809 dev->ops = &default_pci_ops_dev;
811 case PCI_HEADER_TYPE_BRIDGE:
812 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
814 dev->ops = get_pci_bridge_ops(dev);
816 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
817 case PCI_HEADER_TYPE_CARDBUS:
818 dev->ops = &default_cardbus_ops_bus;
824 printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown header "
825 "type %02x, ignoring.\n",
827 dev->vendor, dev->device,
828 dev->class >> 8, dev->hdr_type);
835 * @brief See if we have already allocated a device structure for a given devfn.
837 * Given a linked list of PCI device structures and a devfn number, find the
838 * device structure correspond to the devfn, if present. This function also
839 * removes the device structure from the linked list.
841 * @param list The device structure list.
842 * @param devfn A device/function number.
844 * @return Pointer to the device structure found or NULL if we have not
845 * allocated a device for this devfn yet.
847 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
851 for (; *list; list = &(*list)->sibling) {
852 if ((*list)->path.type != DEVICE_PATH_PCI) {
853 printk(BIOS_ERR, "child %s not a pci device\n",
857 if ((*list)->path.pci.devfn == devfn) {
858 /* Unlink from the list. */
860 *list = (*list)->sibling;
866 /* Just like alloc_dev() add the device to the list of devices on the
867 * bus. When the list of devices was formed we removed all of the
868 * parents children, and now we are interleaving static and dynamic
869 * devices in order on the bus.
872 struct device *child;
873 /* Find the last child of our parent. */
874 for (child = dev->bus->children; child && child->sibling;) {
875 child = child->sibling;
877 /* Place the device on the list of children of its parent. */
879 child->sibling = dev;
881 dev->bus->children = dev;
889 * @brief Scan a PCI bus.
891 * Determine the existence of a given PCI device. Allocate a new struct device
892 * if dev==NULL was passed in and the device exists in hardware.
894 * @param bus pointer to the bus structure
895 * @param devfn to look at
897 * @return The device structure for hte device (if found)
898 * or the NULL if no device is found.
900 device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
905 /* Detect if a device is present. */
909 dummy.path.type = DEVICE_PATH_PCI;
910 dummy.path.pci.devfn = devfn;
911 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
912 /* Have we found something?
913 * Some broken boards return 0 if a slot is empty, but
914 * the expected answer is 0xffffffff
916 if (id == 0xffffffff) {
919 if ((id == 0x00000000) || (id == 0x0000ffff) ||
920 (id == 0xffff0000)) {
921 printk(BIOS_SPEW, "%s, bad id 0x%x\n", dev_path(&dummy), id);
924 dev = alloc_dev(bus, &dummy.path);
926 /* Enable/disable the device. Once we have found the device-
927 * specific operations this operations we will disable the
928 * device with those as well.
930 * This is geared toward devices that have subfunctions
931 * that do not show up by default.
933 * If a device is a stuff option on the motherboard
934 * it may be absent and enable_dev() must cope.
936 /* Run the magic enable sequence for the device. */
937 if (dev->chip_ops && dev->chip_ops->enable_dev) {
938 dev->chip_ops->enable_dev(dev);
940 /* Now read the vendor and device ID. */
941 id = pci_read_config32(dev, PCI_VENDOR_ID);
943 /* If the device does not have a PCI ID disable it. Possibly
944 * this is because we have already disabled the device. But
945 * this also handles optional devices that may not always
948 /* If the chain is fully enumerated quit */
949 if ((id == 0xffffffff) || (id == 0x00000000) ||
950 (id == 0x0000ffff) || (id == 0xffff0000)) {
952 printk(BIOS_INFO, "PCI: Static device %s not found, disabling it.\n",
959 /* Read the rest of the PCI configuration information. */
960 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
961 class = pci_read_config32(dev, PCI_CLASS_REVISION);
963 /* Store the interesting information in the device structure. */
964 dev->vendor = id & 0xffff;
965 dev->device = (id >> 16) & 0xffff;
966 dev->hdr_type = hdr_type;
968 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
969 dev->class = class >> 8;
971 /* Architectural/System devices always need to be bus masters. */
972 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
973 dev->command |= PCI_COMMAND_MASTER;
975 /* Look at the vendor and device ID, or at least the header type and
976 * class and figure out which set of configuration methods to use.
977 * Unless we already have some PCI ops.
981 /* Now run the magic enable/disable sequence for the device. */
982 if (dev->ops && dev->ops->enable) {
983 dev->ops->enable(dev);
986 /* Display the device. */
987 printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n",
989 dev->vendor, dev->device,
990 dev->enabled ? "enabled" : "disabled",
991 dev->ops ? "" : " No operations");
997 * @brief Scan a PCI bus.
999 * Determine the existence of devices and bridges on a PCI bus. If there are
1000 * bridges on the bus, recursively scan the buses behind the bridges.
1002 * This function is the default scan_bus() method for the root device
1005 * @param bus pointer to the bus structure
1006 * @param min_devfn minimum devfn to look at in the scan usually 0x00
1007 * @param max_devfn maximum devfn to look at in the scan usually 0xff
1008 * @param max current bus number
1010 * @return The maximum bus number found, after scanning all subordinate busses
1012 unsigned int pci_scan_bus(struct bus *bus,
1013 unsigned min_devfn, unsigned max_devfn,
1017 struct device *old_devices;
1018 struct device *child;
1020 #if CONFIG_PCI_BUS_SEGN_BITS
1021 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
1022 bus->secondary >> 8, bus->secondary & 0xff);
1024 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1027 old_devices = bus->children;
1028 bus->children = NULL;
1031 /* Probe all devices/functions on this bus with some optimization for
1032 * non-existence and single function devices.
1034 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1037 /* First thing setup the device structure */
1038 dev = pci_scan_get_dev(&old_devices, devfn);
1040 /* See if a device is present and setup the device structure. */
1041 dev = pci_probe_dev(dev, bus, devfn);
1043 /* If this is not a multi function device, or the device is
1044 * not present don't waste time probing another function.
1045 * Skip to next device.
1047 if ((PCI_FUNC(devfn) == 0x00) &&
1049 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1055 /* Warn if any leftover static devices are are found.
1056 * There's probably a problem in the Config.lb.
1060 printk(BIOS_WARNING, "PCI: Left over static devices:\n");
1061 for (left = old_devices; left; left = left->sibling) {
1062 printk(BIOS_WARNING, "%s\n", dev_path(left));
1064 printk(BIOS_WARNING, "PCI: Check your mainboard Config.lb.\n");
1067 /* For all children that implement scan_bus() (i.e. bridges)
1068 * scan the bus behind that child.
1070 for (child = bus->children; child; child = child->sibling) {
1071 max = scan_bus(child, max);
1074 /* We've scanned the bus and so we know all about what's on the other
1075 * side of any bridges that may be on this bus plus any devices.
1076 * Return how far we've got finding sub-buses.
1078 printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
1084 * @brief Scan a PCI bridge and the buses behind the bridge.
1086 * Determine the existence of buses behind the bridge. Set up the bridge
1087 * according to the result of the scan.
1089 * This function is the default scan_bus() method for PCI bridge devices.
1091 * @param dev Pointer to the bridge device.
1092 * @param max The highest bus number assigned up to now.
1093 * @return The maximum bus number found, after scanning all subordinate buses.
1095 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1096 unsigned int (*do_scan_bus) (struct bus * bus,
1105 printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
1107 bus = &dev->link[0];
1111 /* Set up the primary, secondary and subordinate bus numbers. We have
1112 * no idea how many buses are behind this bridge yet, so we set the
1113 * subordinate bus number to 0xff for the moment.
1115 bus->secondary = ++max;
1116 bus->subordinate = 0xff;
1118 /* Clear all status bits and turn off memory, I/O and master enables. */
1119 cr = pci_read_config16(dev, PCI_COMMAND);
1120 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1121 pci_write_config16(dev, PCI_STATUS, 0xffff);
1123 /* Read the existing primary/secondary/subordinate bus
1124 * number configuration.
1126 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1128 /* Configure the bus numbers for this bridge: the configuration
1129 * transactions will not be propagated by the bridge if it is not
1130 * correctly configured.
1132 buses &= 0xff000000;
1133 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1134 ((unsigned int)(bus->secondary) << 8) |
1135 ((unsigned int)(bus->subordinate) << 16));
1136 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1138 /* Now we can scan all subordinate buses
1139 * i.e. the bus behind the bridge.
1141 max = do_scan_bus(bus, 0x00, 0xff, max);
1143 /* We know the number of buses behind this bridge. Set the subordinate
1144 * bus number to its real value.
1146 bus->subordinate = max;
1147 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1148 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1149 pci_write_config16(dev, PCI_COMMAND, cr);
1151 printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
1156 * @brief Scan a PCI bridge and the buses behind the bridge.
1158 * Determine the existence of buses behind the bridge. Set up the bridge
1159 * according to the result of the scan.
1161 * This function is the default scan_bus() method for PCI bridge devices.
1163 * @param dev Pointer to the bridge device.
1164 * @param max The highest bus number assigned up to now.
1165 * @return The maximum bus number found, after scanning all subordinate buses.
1167 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1169 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1173 * @brief Scan a PCI domain.
1175 * This function is the default scan_bus() method for PCI domains.
1177 * @param dev pointer to the domain
1178 * @param max the highest bus number assgined up to now
1180 * @return The maximum bus number found, after scanning all subordinate busses
1182 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1184 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
1188 #if CONFIG_PC80_SYSTEM == 1
1191 * @brief Assign IRQ numbers
1193 * This function assigns IRQs for all functions contained within the indicated
1194 * device address. If the device does not exist or does not require interrupts
1195 * then this function has no effect.
1197 * This function should be called for each PCI slot in your system.
1201 * @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through
1202 * PINTD of this slot. The particular irq #s that are passed in
1203 * depend on the routing inside your southbridge and on your
1206 void pci_assign_irqs(unsigned bus, unsigned slot,
1207 const unsigned char pIntAtoD[4])
1214 /* Each slot may contain up to eight functions */
1215 for (funct = 0; funct < 8; funct++) {
1216 pdev = dev_find_slot(bus, (slot << 3) + funct);
1221 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1223 // PCI spec says all values except 1..4 are reserved.
1224 if ((line < 1) || (line > 4))
1227 irq = pIntAtoD[line - 1];
1229 printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
1230 irq, bus, slot, funct);
1232 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1233 pIntAtoD[line - 1]);
1235 #ifdef PARANOID_IRQ_ASSIGNMENTS
1236 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1237 printk(BIOS_DEBUG, " Readback = %d\n", irq);
1240 // Change to level triggered
1241 i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED);