2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <device/chip.h>
22 #include <part/hard_reset.h>
23 #include <part/fallback_boot.h>
25 /** Given a device and register, read the size of the BAR for that register.
26 * @param dev Pointer to the device structure
27 * @param resource Pointer to the resource structure
28 * @param index Address of the pci configuration register
30 static void pci_get_resource(struct device *dev, struct resource *resource, unsigned long index)
32 uint32_t addr, size, base;
35 /* Initialize the resources to nothing */
42 resource->index = index;
44 addr = pci_read_config32(dev, index);
46 /* FIXME: more consideration for 64-bit PCI devices,
47 * we currently detect their size but otherwise
48 * treat them as 32-bit resources
51 pci_write_config32(dev, index, ~0);
52 size = pci_read_config32(dev, index);
54 /* get the minimum value the bar can be set to */
55 pci_write_config32(dev, index, 0);
56 base = pci_read_config32(dev, index);
59 pci_write_config32(dev, index, addr);
62 * some broken hardware has read-only registers that do not
63 * really size correctly. You can tell this if addr == size
64 * Example: the acer m7229 has BARs 1-4 normally read-only.
65 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
66 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
67 * violation of the spec.
68 * We catch this case and ignore it by settting size and type to 0.
69 * This incidentally catches the common case where registers
70 * read back as 0 for both address and size.
72 if ((addr == size) && (addr == base)) {
75 "%s register %02x(%08x), read-only ignoring it\n",
81 /* Now compute the actual size, See PCI Spec 6.2.5.1 ... */
82 else if (size & PCI_BASE_ADDRESS_SPACE_IO) {
83 type = size & (~PCI_BASE_ADDRESS_IO_MASK);
84 /* BUG! Top 16 bits can be zero (or not)
85 * So set them to 0xffff so they go away ...
87 resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1;
88 resource->align = log2(resource->size);
89 resource->gran = resource->align;
90 resource->flags = IORESOURCE_IO;
91 resource->limit = 0xffff;
94 /* A Memory mapped base address */
95 type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
96 resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1;
97 resource->align = log2(resource->size);
98 resource->gran = resource->align;
99 resource->flags = IORESOURCE_MEM;
100 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
101 resource->flags |= IORESOURCE_PREFETCH;
103 type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
104 if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) {
106 resource->limit = 0xffffffffUL;
108 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) {
110 resource->limit = 0x000fffffUL;
112 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
113 unsigned long index_hi;
115 * For now just treat this as a 32bit limit
117 index_hi = index + 4;
118 resource->limit = 0xffffffffUL;
119 resource->flags |= IORESOURCE_PCI64;
120 addr = pci_read_config32( dev, index_hi);
121 /* get the extended size */
122 pci_write_config32(dev, index_hi, 0xffffffffUL);
123 size = pci_read_config32( dev, index_hi);
125 /* get the minimum value the bar can be set to */
126 pci_write_config32(dev, index_hi, 0);
127 base = pci_read_config32(dev, index_hi);
130 pci_write_config32(dev, index_hi, addr);
132 if ((size == 0xffffffff) && (base == 0)) {
133 /* Clear the top half of the bar */
134 pci_write_config32(dev, index_hi, 0);
137 printk_err("%s Unable to handle 64-bit address\n",
139 resource->flags = IORESOURCE_PCI64;
147 /* dev->size holds the flags... */
151 /** Read the base address registers for a given device.
152 * @param dev Pointer to the dev structure
153 * @param howmany How many registers to read (6 for device, 2 for bridge)
155 static void pci_read_bases(struct device *dev, unsigned int howmany)
160 reg = dev->resources;
161 for(index = PCI_BASE_ADDRESS_0;
162 (reg < MAX_RESOURCES) && (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
163 struct resource *resource;
164 resource = &dev->resource[reg];
165 pci_get_resource(dev, resource, index);
166 reg += (resource->flags & (IORESOURCE_IO | IORESOURCE_MEM))? 1:0;
167 index += (resource->flags & IORESOURCE_PCI64)?8:4;
169 dev->resources = reg;
173 static void pci_bridge_read_bases(struct device *dev)
175 unsigned int reg = dev->resources;
177 /* FIXME handle bridges without some of the optional resources */
179 /* Initialize the io space constraints on the current bus */
180 dev->resource[reg].base = 0;
181 dev->resource[reg].size = 0;
182 dev->resource[reg].align = log2(PCI_IO_BRIDGE_ALIGN);
183 dev->resource[reg].gran = log2(PCI_IO_BRIDGE_ALIGN);
184 dev->resource[reg].limit = 0xffffUL;
185 dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_PCI_BRIDGE;
186 dev->resource[reg].index = PCI_IO_BASE;
187 compute_allocate_resource(&dev->link[0], &dev->resource[reg],
188 IORESOURCE_IO, IORESOURCE_IO);
191 /* Initiliaze the prefetchable memory constraints on the current bus */
192 dev->resource[reg].base = 0;
193 dev->resource[reg].size = 0;
194 dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
195 dev->resource[reg].gran = log2(PCI_MEM_BRIDGE_ALIGN);
196 dev->resource[reg].limit = 0xffffffffUL;
197 dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE;
198 dev->resource[reg].index = PCI_PREF_MEMORY_BASE;
199 compute_allocate_resource(&dev->link[0], &dev->resource[reg],
200 IORESOURCE_MEM | IORESOURCE_PREFETCH,
201 IORESOURCE_MEM | IORESOURCE_PREFETCH);
204 /* Initialize the memory resources on the current bus */
205 dev->resource[reg].base = 0;
206 dev->resource[reg].size = 0;
207 dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
208 dev->resource[reg].gran = log2(PCI_MEM_BRIDGE_ALIGN);
209 dev->resource[reg].limit = 0xffffffffUL;
210 dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE;
211 dev->resource[reg].index = PCI_MEMORY_BASE;
212 compute_allocate_resource(&dev->link[0], &dev->resource[reg],
213 IORESOURCE_MEM | IORESOURCE_PREFETCH,
217 dev->resources = reg;
221 void pci_dev_read_resources(struct device *dev)
225 memset(&dev->resource[0], 0, sizeof(dev->resource));
226 pci_read_bases(dev, 6);
227 addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
228 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
231 void pci_bus_read_resources(struct device *dev)
235 memset(&dev->resource, 0, sizeof(dev->resource));
236 pci_bridge_read_bases(dev);
237 pci_read_bases(dev, 2);
239 addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
240 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
245 static void pci_set_resource(struct device *dev, struct resource *resource)
247 unsigned long base, limit;
248 unsigned char buf[10];
251 /* Make certain the resource has actually been set */
252 if (!(resource->flags & IORESOURCE_SET)) {
254 printk_err("ERROR: %s %02x not allocated\n",
255 dev_path(dev), resource->index);
260 /* Only handle PCI memory and IO resources for now */
261 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
264 if (resource->flags & IORESOURCE_MEM) {
265 dev->command |= PCI_COMMAND_MEMORY;
267 if (resource->flags & IORESOURCE_IO) {
268 dev->command |= PCI_COMMAND_IO;
270 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
271 dev->command |= PCI_COMMAND_MASTER;
273 /* Get the base address */
274 base = resource->base;
275 /* Get the resource alignment */
276 align = 1UL << resource->align;
278 /* Get the limit (rounded up) */
279 limit = base + ((resource->size + align - 1UL) & ~(align - 1UL)) -1UL;
281 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
283 * some chipsets allow us to set/clear the IO bit.
284 * (e.g. VIA 82c686a.) So set it to be safe)
286 limit = base + resource->size -1;
287 if (resource->flags & IORESOURCE_IO) {
288 base |= PCI_BASE_ADDRESS_SPACE_IO;
290 pci_write_config32(dev, resource->index, base & 0xffffffff);
291 if (resource->flags & IORESOURCE_PCI64) {
292 /* FIXME handle real 64bit base addresses */
293 pci_write_config32(dev, resource->index + 4, 0);
296 else if (resource->index == PCI_IO_BASE) {
298 * WARNING: we don't really do 32-bit addressing for IO yet!
300 compute_allocate_resource(&dev->link[0], resource,
301 IORESOURCE_IO, IORESOURCE_IO);
302 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
303 pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
304 pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0);
305 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0);
307 else if (resource->index == PCI_MEMORY_BASE) {
308 /* set the memory range
310 compute_allocate_resource(&dev->link[0], resource,
311 IORESOURCE_MEM | IORESOURCE_PREFETCH,
313 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
314 pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
316 else if (resource->index == PCI_PREF_MEMORY_BASE) {
317 /* set the prefetchable memory range
318 * WARNING: we don't really do 64-bit addressing for prefetchable memory yet!
320 compute_allocate_resource(&dev->link[0], resource,
321 IORESOURCE_MEM | IORESOURCE_PREFETCH,
322 IORESOURCE_MEM | IORESOURCE_PREFETCH);
323 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
324 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
325 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0);
326 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0);
329 printk_err("ERROR: invalid resource->index %x\n",
333 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
334 sprintf(buf, "bus %d ", dev->link[0].secondary);
338 "%s %02x <- [0x%08lx - 0x%08lx] %s%s\n",
341 resource->base, limit,
343 (resource->flags & IORESOURCE_IO)? "io":
344 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
348 void pci_dev_set_resources(struct device *dev)
350 struct resource *resource, *last;
354 last = &dev->resource[dev->resources];
356 for(resource = &dev->resource[0]; resource < last; resource++) {
357 pci_set_resource(dev, resource);
359 for(link = 0; link < dev->links; link++) {
361 bus = &dev->link[link];
363 assign_resources(bus);
367 /* set a default latency timer */
368 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
370 /* set a default secondary latency timer */
371 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
372 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
375 /* zero the irq settings */
376 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
378 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
380 /* set the cache line size, so far 64 bytes is good for everyone */
381 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
384 void pci_dev_enable_resources(struct device *dev)
387 command = pci_read_config16(dev, PCI_COMMAND);
388 command |= dev->command;
389 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
390 pci_write_config16(dev, PCI_COMMAND, command);
392 enable_childrens_resources(dev);
395 void pci_bus_enable_resources(struct device *dev)
398 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
399 ctrl |= dev->link[0].bridge_ctrl;
400 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
401 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
403 pci_dev_enable_resources(dev);
406 struct device_operations default_pci_ops_dev = {
407 .read_resources = pci_dev_read_resources,
408 .set_resources = pci_dev_set_resources,
409 .enable_resources = pci_dev_enable_resources,
413 struct device_operations default_pci_ops_bus = {
414 .read_resources = pci_bus_read_resources,
415 .set_resources = pci_dev_set_resources,
416 .enable_resources = pci_bus_enable_resources,
418 .scan_bus = pci_scan_bridge,
420 static void set_pci_ops(struct device *dev)
422 struct pci_driver *driver;
426 /* Look through the list of setup drivers and find one for
429 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
430 if ((driver->vendor == dev->vendor) &&
431 (driver->device == dev->device)) {
432 dev->ops = driver->ops;
434 printk_debug("%s [%04x/%04x] %sops\n",
436 driver->vendor, driver->device,
437 (driver->ops->scan_bus?"bus ":"")
443 /* If I don't have a specific driver use the default operations */
444 switch(dev->hdr_type & 0x7f) { /* header type */
445 case PCI_HEADER_TYPE_NORMAL: /* standard header */
446 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
448 dev->ops = &default_pci_ops_dev;
450 case PCI_HEADER_TYPE_BRIDGE:
451 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
453 dev->ops = &default_pci_ops_bus;
458 printk_err("%s [%04x/%04x/%06x] has unknown header "
459 "type %02x, ignoring.\n",
461 dev->vendor, dev->device,
462 dev->class >> 8, dev->hdr_type);
469 * Given a bus and a devfn number, find the device structure
470 * @param bus The bus structure
471 * @param devfn a device/function number
472 * @return pointer to the device structure
474 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
476 struct device *dev = 0;
477 for(; *list; list = &(*list)->sibling) {
478 if ((*list)->path.type != DEVICE_PATH_PCI) {
479 printk_err("child %s not a pci device\n", dev_path(*list));
482 if ((*list)->path.u.pci.devfn == devfn) {
483 /* Unlink from the list */
485 *list = (*list)->sibling;
492 /* Find the last child of our parent */
493 for(child = dev->bus->children; child && child->sibling; ) {
494 child = child->sibling;
496 /* Place the device on the list of children of it's parent. */
498 child->sibling = dev;
500 dev->bus->children = dev;
507 /** Scan the pci bus devices and bridges.
508 * @param bus pointer to the bus structure
509 * @param min_devfn minimum devfn to look at in the scan usually 0x00
510 * @param max_devfn maximum devfn to look at in the scan usually 0xff
511 * @param max current bus number
512 * @return The maximum bus number found, after scanning all subordinate busses
514 unsigned int pci_scan_bus(struct bus *bus,
515 unsigned min_devfn, unsigned max_devfn,
520 device_t old_devices;
523 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
525 old_devices = bus->children;
531 /* probe all devices on this bus with some optimization for non-existance and
532 single funcion devices */
533 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
537 /* First thing setup the device structure */
538 dev = pci_scan_get_dev(&old_devices, devfn);
540 /* Detect if a device is present */
544 dummy.path.type = DEVICE_PATH_PCI;
545 dummy.path.u.pci.devfn = devfn;
546 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
547 /* some broken boards return 0 if a slot is empty: */
548 if ( (id == 0xffffffff) || (id == 0x00000000) ||
549 (id == 0x0000ffff) || (id == 0xffff0000))
551 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
552 if (PCI_FUNC(devfn) == 0x00) {
553 /* if this is a function 0 device and it is not present,
554 skip to next device */
557 /* multi function device, skip to next function */
560 dev = alloc_dev(bus, &dummy.path);
563 /* Run the magic enable/disable sequence for the device */
564 if (dev->chip && dev->chip->control && dev->chip->control->enable_dev) {
565 dev->chip->control->enable_dev(dev);
567 /* Now read the vendor and device id */
568 id = pci_read_config32(dev, PCI_VENDOR_ID);
570 /* Read the rest of the pci configuration information */
571 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
572 class = pci_read_config32(dev, PCI_CLASS_REVISION);
574 /* Store the interesting information in the device structure */
575 dev->vendor = id & 0xffff;
576 dev->device = (id >> 16) & 0xffff;
577 dev->hdr_type = hdr_type;
578 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
579 dev->class = class >> 8;
581 /* Look at the vendor and device id, or at least the
582 * header type and class and figure out which set of configuration
583 * methods to use. Unless we already have some pci ops.
586 /* Error if we don't have some pci operations for it */
587 if (dev->enable && !dev->ops) {
588 printk_err("%s No device operations\n",
593 /* Now run the magic enable/disable sequence for the device */
594 if (dev->ops && dev->ops->enable) {
595 dev->ops->enable(dev);
598 printk_debug("%s [%04x/%04x] %s\n",
600 dev->vendor, dev->device,
601 dev->enable?"enabled": "disabled");
603 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
604 /* if this is not a multi function device, don't waste time probe
605 another function. Skip to next device. */
611 for(child = bus->children; child; child = child->sibling) {
612 if (!child->ops->scan_bus) {
615 max = child->ops->scan_bus(child, max);
618 * We've scanned the bus and so we know all about what's on
619 * the other side of any bridges that may be on this bus plus
622 * Return how far we've got finding sub-buses.
624 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
629 /** Scan the bus, first for bridges and next for devices.
630 * @param pci_bus pointer to the bus structure
631 * @return The maximum bus number found, after scanning all subordinate busses
633 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
642 /* Set up the primary, secondary and subordinate bus numbers. We have
643 * no idea how many buses are behind this bridge yet, so we set the
644 * subordinate bus number to 0xff for the moment
646 bus->secondary = ++max;
647 bus->subordinate = 0xff;
649 /* Clear all status bits and turn off memory, I/O and master enables. */
650 cr = pci_read_config16(dev, PCI_COMMAND);
651 pci_write_config16(dev, PCI_COMMAND, 0x0000);
652 pci_write_config16(dev, PCI_STATUS, 0xffff);
655 * Read the existing primary/secondary/subordinate bus
656 * number configuration.
658 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
660 /* Configure the bus numbers for this bridge: the configuration
661 * transactions will not be propagated by the bridge if it is not
662 * correctly configured
665 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
666 ((unsigned int) (bus->secondary) << 8) |
667 ((unsigned int) (bus->subordinate) << 16));
668 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
670 /* Now we can scan all subordinate buses i.e. the bus hehind the bridge */
671 max = pci_scan_bus(bus, 0x00, 0xff, max);
673 /* We know the number of buses behind this bridge. Set the subordinate
674 * bus number to its real value
676 bus->subordinate = max;
677 buses = (buses & 0xff00ffff) |
678 ((unsigned int) (bus->subordinate) << 16);
679 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
680 pci_write_config16(dev, PCI_COMMAND, cr);
682 printk_spew("%s returns max %d\n", __FUNCTION__, max);
686 Tell the EISA int controller this int must be level triggered
687 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
689 static void pci_level_irq(unsigned char intNum)
691 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
693 printk_spew("%s: current ints are 0x%x\n", __FUNCTION__, intBits);
694 intBits |= (1 << intNum);
696 printk_spew("%s: try to set ints 0x%x\n", __FUNCTION__, intBits);
699 outb((unsigned char) intBits, 0x4d0);
700 outb((unsigned char) (intBits >> 8), 0x4d1);
702 /* this seems like an error but is not ... */
704 if (inb(0x4d0) != (intBits & 0xf)) {
705 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
706 __FUNCTION__, intBits &0xf, inb(0x4d0));
708 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
709 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
710 __FUNCTION__, (intBits>>8) &0xf, inb(0x4d1));
716 This function assigns IRQs for all functions contained within
717 the indicated device address. If the device does not exist or does
718 not require interrupts then this function has no effect.
720 This function should be called for each PCI slot in your system.
722 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
724 The particular irq #s that are passed in depend on the routing inside
725 your southbridge and on your motherboard.
729 void pci_assign_irqs(unsigned bus, unsigned slot,
730 const unsigned char pIntAtoD[4])
736 unsigned char readback;
738 /* Each slot may contain up to eight functions */
739 for (functNum = 0; functNum < 8; functNum++) {
740 pdev = dev_find_slot(bus, (slot << 3) + functNum);
743 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
745 // PCI spec says all other values are reserved
746 if ((line >= 1) && (line <= 4)) {
747 irq = pIntAtoD[line - 1];
749 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
750 irq, bus, slot, functNum);
752 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
755 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
756 printk_debug(" Readback = %d\n", readback);
758 // Change to level triggered
759 pci_level_irq(pIntAtoD[line - 1]);