2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <device/chip.h>
22 #include <part/hard_reset.h>
23 #include <part/fallback_boot.h>
26 static uint8_t pci_moving_config8(struct device *dev, unsigned reg)
28 uint8_t value, ones, zeroes;
29 value = pci_read_config8(dev, reg);
31 pci_write_config8(dev, reg, 0xff);
32 ones = pci_read_config8(dev, reg);
34 pci_write_config8(dev, reg, 0x00);
35 zeroes = pci_read_config8(dev, reg);
37 pci_write_config8(dev, reg, value);
41 static uint16_t pci_moving_config16(struct device *dev, unsigned reg)
43 uint16_t value, ones, zeroes;
44 value = pci_read_config16(dev, reg);
46 pci_write_config16(dev, reg, 0xffff);
47 ones = pci_read_config16(dev, reg);
49 pci_write_config16(dev, reg, 0x0000);
50 zeroes = pci_read_config16(dev, reg);
52 pci_write_config16(dev, reg, value);
56 static uint32_t pci_moving_config32(struct device *dev, unsigned reg)
58 uint32_t value, ones, zeroes;
59 value = pci_read_config32(dev, reg);
61 pci_write_config32(dev, reg, 0xffffffff);
62 ones = pci_read_config32(dev, reg);
64 pci_write_config32(dev, reg, 0x00000000);
65 zeroes = pci_read_config32(dev, reg);
67 pci_write_config32(dev, reg, value);
72 unsigned pci_find_capability(device_t dev, unsigned cap)
76 switch(dev->hdr_type & 0x7f) {
77 case PCI_HEADER_TYPE_NORMAL:
78 case PCI_HEADER_TYPE_BRIDGE:
79 pos = PCI_CAPABILITY_LIST;
82 if (pos > PCI_CAP_LIST_NEXT) {
83 pos = pci_read_config8(dev, pos);
85 while(pos != 0) { /* loop through the linked list */
87 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
88 if (this_cap == cap) {
96 /** Given a device and register, read the size of the BAR for that register.
97 * @param dev Pointer to the device structure
98 * @param resource Pointer to the resource structure
99 * @param index Address of the pci configuration register
101 struct resource *pci_get_resource(struct device *dev, unsigned long index)
103 struct resource *resource;
104 unsigned long value, attr;
105 resource_t moving, limit;
107 /* Initialize the resources to nothing */
108 resource = new_resource(dev, index);
110 /* Get the initial value */
111 value = pci_read_config32(dev, index);
113 /* See which bits move */
114 moving = pci_moving_config32(dev, index);
116 /* Initialize attr to the bits that do not move */
117 attr = value & ~moving;
119 /* If it is a 64bit resource look at the high half as well */
120 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
121 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
123 /* Find the high bits that move */
124 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
126 /* Find the resource constraints.
128 * Start by finding the bits that move. From there:
129 * - Size is the least significant bit of the bits that move.
130 * - Limit is all of the bits that move plus all of the lower bits.
131 * See PCI Spec 6.2.5.1 ...
136 resource->align = resource->gran = 0;
137 while(!(moving & resource->size)) {
138 resource->size <<= 1;
139 resource->align += 1;
142 resource->limit = limit = moving | (resource->size - 1);
145 * some broken hardware has read-only registers that do not
146 * really size correctly.
147 * Example: the acer m7229 has BARs 1-4 normally read-only.
148 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
149 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
150 * violation of the spec.
151 * We catch this case and ignore it by observing which bits move,
152 * This also catches the common case unimplemented registers
153 * that always read back as 0.
158 "%s register %02x(%08x), read-only ignoring it\n",
159 dev_path(dev), index, value);
163 else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
164 /* An I/O mapped base address */
165 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
166 resource->flags |= IORESOURCE_IO;
167 /* I don't want to deal with 32bit I/O resources */
168 resource->limit = 0xffff;
171 /* A Memory mapped base address */
172 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
173 resource->flags |= IORESOURCE_MEM;
174 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
175 resource->flags |= IORESOURCE_PREFETCH;
177 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
178 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
180 resource->limit = 0xffffffffUL;
182 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
184 resource->limit = 0x000fffffUL;
186 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
188 resource->limit = 0xffffffffffffffffULL;
189 resource->flags |= IORESOURCE_PCI64;
196 /* Don't let the limit exceed which bits can move */
197 if (resource->limit > limit) {
198 resource->limit = limit;
201 if (resource->flags) {
202 printk_debug("%s %02x ->",
203 dev_path(dev), resource->index);
204 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
205 value, zeroes, ones, attr);
207 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s%s\n ",
210 resource->size, resource->limit,
211 (resource->flags == 0) ? "unused":
212 (resource->flags & IORESOURCE_IO)? "io":
213 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem",
214 (resource->flags & IORESOURCE_PCI64)?"64":"");
221 /** Read the base address registers for a given device.
222 * @param dev Pointer to the dev structure
223 * @param howmany How many registers to read (6 for device, 2 for bridge)
225 static void pci_read_bases(struct device *dev, unsigned int howmany)
229 for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
230 struct resource *resource;
231 resource = pci_get_resource(dev, index);
232 index += (resource->flags & IORESOURCE_PCI64)?8:4;
234 compact_resources(dev);
237 static void pci_set_resource(struct device *dev, struct resource *resource);
239 static void pci_record_bridge_resource(
240 struct device *dev, resource_t moving,
241 unsigned index, unsigned long mask, unsigned long type)
243 /* Initiliaze the constraints on the current bus */
244 struct resource *resource;
249 resource = new_resource(dev, index);
253 while((moving & step) == 0) {
257 resource->gran = gran;
258 resource->align = gran;
259 resource->limit = moving | (step - 1);
260 resource->flags = type | IORESOURCE_PCI_BRIDGE;
261 compute_allocate_resource(&dev->link[0], resource, mask, type);
262 /* If there is nothing behind the resource,
263 * clear it and forget it.
265 if (resource->size == 0) {
266 resource->base = moving;
267 resource->flags |= IORESOURCE_ASSIGNED;
268 resource->flags &= ~IORESOURCE_STORED;
269 pci_set_resource(dev, resource);
277 static void pci_bridge_read_bases(struct device *dev)
279 resource_t moving_base, moving_limit, moving;
282 /* See if the bridge I/O resources are implemented */
283 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
284 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
286 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
287 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
289 moving = moving_base & moving_limit;
291 /* Initialize the io space constraints on the current bus */
292 pci_record_bridge_resource(
293 dev, moving, PCI_IO_BASE,
294 IORESOURCE_IO, IORESOURCE_IO);
297 /* See if the bridge prefmem resources are implemented */
298 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
299 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
301 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
302 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
304 moving = moving_base & moving_limit;
305 /* Initiliaze the prefetchable memory constraints on the current bus */
306 pci_record_bridge_resource(
307 dev, moving, PCI_PREF_MEMORY_BASE,
308 IORESOURCE_MEM | IORESOURCE_PREFETCH,
309 IORESOURCE_MEM | IORESOURCE_PREFETCH);
312 /* See if the bridge mem resources are implemented */
313 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
314 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
316 moving = moving_base & moving_limit;
318 /* Initialize the memory resources on the current bus */
319 pci_record_bridge_resource(
320 dev, moving, PCI_MEMORY_BASE,
321 IORESOURCE_MEM | IORESOURCE_PREFETCH,
324 compact_resources(dev);
327 void pci_dev_read_resources(struct device *dev)
331 pci_read_bases(dev, 6);
333 addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
334 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
337 void pci_bus_read_resources(struct device *dev)
341 pci_bridge_read_bases(dev);
342 pci_read_bases(dev, 2);
344 addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
345 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
348 static void pci_set_resource(struct device *dev, struct resource *resource)
350 resource_t base, end;
352 /* Make certain the resource has actually been set */
353 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
354 printk_err("ERROR: %s %02x not allocated\n",
355 dev_path(dev), resource->index);
359 /* If I have already stored this resource don't worry about it */
360 if (resource->flags & IORESOURCE_STORED) {
364 /* If the resources is substractive don't worry about it */
365 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
369 /* Only handle PCI memory and IO resources for now */
370 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
373 /* Enable the resources in the command register */
374 if (resource->size) {
375 if (resource->flags & IORESOURCE_MEM) {
376 dev->command |= PCI_COMMAND_MEMORY;
378 if (resource->flags & IORESOURCE_IO) {
379 dev->command |= PCI_COMMAND_IO;
381 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
382 dev->command |= PCI_COMMAND_MASTER;
385 /* Get the base address */
386 base = resource->base;
389 end = resource_end(resource);
391 /* Now store the resource */
392 resource->flags |= IORESOURCE_STORED;
393 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
394 unsigned long base_lo, base_hi;
396 * some chipsets allow us to set/clear the IO bit.
397 * (e.g. VIA 82c686a.) So set it to be safe)
399 base_lo = base & 0xffffffff;
400 base_hi = (base >> 32) & 0xffffffff;
401 if (resource->flags & IORESOURCE_IO) {
402 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
404 pci_write_config32(dev, resource->index, base_lo);
405 if (resource->flags & IORESOURCE_PCI64) {
406 pci_write_config32(dev, resource->index + 4, base_hi);
409 else if (resource->index == PCI_IO_BASE) {
410 /* set the IO ranges */
411 compute_allocate_resource(&dev->link[0], resource,
412 IORESOURCE_IO, IORESOURCE_IO);
413 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
414 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
415 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
416 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
418 else if (resource->index == PCI_MEMORY_BASE) {
419 /* set the memory range */
420 compute_allocate_resource(&dev->link[0], resource,
421 IORESOURCE_MEM | IORESOURCE_PREFETCH,
423 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
424 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
426 else if (resource->index == PCI_PREF_MEMORY_BASE) {
427 /* set the prefetchable memory range */
428 compute_allocate_resource(&dev->link[0], resource,
429 IORESOURCE_MEM | IORESOURCE_PREFETCH,
430 IORESOURCE_MEM | IORESOURCE_PREFETCH);
431 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
432 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
433 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
434 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
437 /* Don't let me think I stored the resource */
438 resource->flags &= ~IORESOURCE_STORED;
439 printk_err("ERROR: invalid resource->index %x\n",
442 report_resource_stored(dev, resource, "");
446 void pci_dev_set_resources(struct device *dev)
448 struct resource *resource, *last;
452 last = &dev->resource[dev->resources];
454 for(resource = &dev->resource[0]; resource < last; resource++) {
455 pci_set_resource(dev, resource);
457 for(link = 0; link < dev->links; link++) {
459 bus = &dev->link[link];
461 assign_resources(bus);
465 /* set a default latency timer */
466 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
468 /* set a default secondary latency timer */
469 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
470 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
473 /* zero the irq settings */
474 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
476 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
478 /* set the cache line size, so far 64 bytes is good for everyone */
479 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
482 void pci_dev_enable_resources(struct device *dev)
484 struct pci_operations *ops;
487 /* Set the subsystem vendor and device id for mainboard devices */
489 if (dev->chip && ops && ops->set_subsystem) {
490 printk_debug("%s subsystem <- %02x/%02x\n",
492 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
493 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
494 ops->set_subsystem(dev,
495 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
496 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
498 command = pci_read_config16(dev, PCI_COMMAND);
499 command |= dev->command;
500 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
501 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
502 pci_write_config16(dev, PCI_COMMAND, command);
504 enable_childrens_resources(dev);
507 void pci_bus_enable_resources(struct device *dev)
510 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
511 ctrl |= dev->link[0].bridge_ctrl;
512 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
513 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
514 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
516 pci_dev_enable_resources(dev);
519 static void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
521 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
522 ((device & 0xffff) << 16) | (vendor & 0xffff));
525 /** Default device operation for PCI devices */
526 static struct pci_operations pci_ops_pci_dev = {
527 .set_subsystem = pci_dev_set_subsystem,
530 struct device_operations default_pci_ops_dev = {
531 .read_resources = pci_dev_read_resources,
532 .set_resources = pci_dev_set_resources,
533 .enable_resources = pci_dev_enable_resources,
537 .ops_pci = &pci_ops_pci_dev,
540 /** Default device operations for PCI bridges */
541 static struct pci_operations pci_ops_pci_bus = {
544 struct device_operations default_pci_ops_bus = {
545 .read_resources = pci_bus_read_resources,
546 .set_resources = pci_dev_set_resources,
547 .enable_resources = pci_bus_enable_resources,
549 .scan_bus = pci_scan_bridge,
551 .ops_pci = &pci_ops_pci_bus,
555 * @brief Set up PCI device operation
562 static void set_pci_ops(struct device *dev)
564 struct pci_driver *driver;
569 /* Look through the list of setup drivers and find one for
572 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
573 if ((driver->vendor == dev->vendor) &&
574 (driver->device == dev->device))
576 dev->ops = driver->ops;
577 printk_debug("%s [%04x/%04x] %sops\n",
579 driver->vendor, driver->device,
580 (driver->ops->scan_bus?"bus ":""));
585 /* If I don't have a specific driver use the default operations */
586 switch(dev->hdr_type & 0x7f) { /* header type */
587 case PCI_HEADER_TYPE_NORMAL: /* standard header */
588 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
590 dev->ops = &default_pci_ops_dev;
592 case PCI_HEADER_TYPE_BRIDGE:
593 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
595 dev->ops = &default_pci_ops_bus;
600 printk_err("%s [%04x/%04x/%06x] has unknown header "
601 "type %02x, ignoring.\n",
603 dev->vendor, dev->device,
604 dev->class >> 8, dev->hdr_type);
611 * @brief See if we have already allocated a device structure for a given devfn.
613 * Given a linked list of PCI device structures and a devfn number, find the
614 * device structure correspond to the devfn, if present.
616 * @param list the device structure list
617 * @param devfn a device/function number
619 * @return pointer to the device structure found or null of we have not allocated
620 * a device for this devfn yet.
622 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
626 for(; *list; list = &(*list)->sibling) {
627 if ((*list)->path.type != DEVICE_PATH_PCI) {
628 printk_err("child %s not a pci device\n",
632 if ((*list)->path.u.pci.devfn == devfn) {
633 /* Unlink from the list */
635 *list = (*list)->sibling;
640 /* Just like alloc_dev add the device to the
641 * list of device on the bus. When the list of devices was formed
642 * we removed all of the parents children, and now we are interleaving
643 * static and dynamic devices in order on the bus.
647 /* Find the last child of our parent */
648 for(child = dev->bus->children; child && child->sibling; ) {
649 child = child->sibling;
651 /* Place the device on the list of children of it's parent. */
653 child->sibling = dev;
655 dev->bus->children = dev;
663 * @brief Scan a PCI bus.
665 * Determine the existence of devices and bridges on a PCI bus. If there are
666 * bridges on the bus, recursively scan the buses behind the bridges.
668 * This function is the default scan_bus() method for the root device
671 * @param bus pointer to the bus structure
672 * @param min_devfn minimum devfn to look at in the scan usually 0x00
673 * @param max_devfn maximum devfn to look at in the scan usually 0xff
674 * @param max current bus number
676 * @return The maximum bus number found, after scanning all subordinate busses
678 unsigned int pci_scan_bus(struct bus *bus,
679 unsigned min_devfn, unsigned max_devfn,
684 device_t old_devices;
687 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
689 old_devices = bus->children;
694 /* probe all devices/functions on this bus with some optimization for
695 * non-existence and single funcion devices
697 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
701 /* First thing setup the device structure */
702 dev = pci_scan_get_dev(&old_devices, devfn);
704 /* Detect if a device is present */
708 dummy.path.type = DEVICE_PATH_PCI;
709 dummy.path.u.pci.devfn = devfn;
710 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
711 /* some broken boards return 0 if a slot is empty: */
712 if ( (id == 0xffffffff) || (id == 0x00000000) ||
713 (id == 0x0000ffff) || (id == 0xffff0000))
715 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
716 if (PCI_FUNC(devfn) == 0x00) {
717 /* if this is a function 0 device and
719 * skip to next device
723 /* This function in a multi function device is
724 * not present, skip to the next function.
728 dev = alloc_dev(bus, &dummy.path);
731 /* Enable/disable the device. Once we have
732 * found the device specific operations this
733 * operations we will disable the device with
736 * This is geared toward devices that have subfunctions
737 * that do not show up by default.
739 * If a device is a stuff option on the motherboard
740 * it may be absent and enable_dev must cope.
743 if ( dev->chip && dev->chip->control &&
744 dev->chip->control->enable_dev)
746 dev->chip->control->enable_dev(dev);
748 /* Now read the vendor and device id */
749 id = pci_read_config32(dev, PCI_VENDOR_ID);
751 /* If the device does not have a pci id disable it.
752 * Possibly this is because we have already disabled
753 * the device. But this also handles optional devices
754 * that may not always show up.
756 if (id == 0xffffffff || id == 0x00000000 ||
757 id == 0x0000ffff || id == 0xffff0000)
760 printk_info("Disabling static device: %s\n",
766 /* Read the rest of the pci configuration information */
767 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
768 class = pci_read_config32(dev, PCI_CLASS_REVISION);
770 /* Store the interesting information in the device structure */
771 dev->vendor = id & 0xffff;
772 dev->device = (id >> 16) & 0xffff;
773 dev->hdr_type = hdr_type;
774 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
775 dev->class = class >> 8;
777 /* Architectural/System devices always need to
780 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
781 dev->command |= PCI_COMMAND_MASTER;
784 /* Look at the vendor and device id, or at least the
785 * header type and class and figure out which set of
786 * configuration methods to use. Unless we already
790 /* Error if we don't have some pci operations for it */
792 printk_err("%s No device operations\n",
797 /* Now run the magic enable/disable sequence for the device */
798 if (dev->ops && dev->ops->enable) {
799 dev->ops->enable(dev);
802 printk_debug("%s [%04x/%04x] %s\n",
804 dev->vendor, dev->device,
805 dev->enabled?"enabled": "disabled");
807 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
808 /* if this is not a multi function device,
809 * don't waste time probing another function.
810 * Skip to next device.
817 /* For all children that implement scan_bus (i.e. bridges)
818 * scan the bus behind that child.
820 for(child = bus->children; child; child = child->sibling) {
821 if (!child->enabled ||
823 !child->ops->scan_bus)
827 max = child->ops->scan_bus(child, max);
831 * We've scanned the bus and so we know all about what's on
832 * the other side of any bridges that may be on this bus plus
835 * Return how far we've got finding sub-buses.
837 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
843 * @brief Scan a PCI bridge and the buses behind the bridge.
845 * Determine the existence of buses behind the bridge. Set up the bridge
846 * according to the result of the scan.
848 * This function is the default scan_bus() method for PCI bridge devices.
850 * @param dev pointer to the bridge device
851 * @param max the highest bus number assgined up to now
853 * @return The maximum bus number found, after scanning all subordinate busses
855 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
864 /* Set up the primary, secondary and subordinate bus numbers. We have
865 * no idea how many buses are behind this bridge yet, so we set the
866 * subordinate bus number to 0xff for the moment.
868 bus->secondary = ++max;
869 bus->subordinate = 0xff;
871 /* Clear all status bits and turn off memory, I/O and master enables. */
872 cr = pci_read_config16(dev, PCI_COMMAND);
873 pci_write_config16(dev, PCI_COMMAND, 0x0000);
874 pci_write_config16(dev, PCI_STATUS, 0xffff);
877 * Read the existing primary/secondary/subordinate bus
878 * number configuration.
880 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
882 /* Configure the bus numbers for this bridge: the configuration
883 * transactions will not be propagated by the bridge if it is not
884 * correctly configured.
887 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
888 ((unsigned int) (bus->secondary) << 8) |
889 ((unsigned int) (bus->subordinate) << 16));
890 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
892 /* Now we can scan all subordinate buses
893 * i.e. the bus behind the bridge.
895 max = pci_scan_bus(bus, 0x00, 0xff, max);
897 /* We know the number of buses behind this bridge. Set the subordinate
898 * bus number to its real value.
900 bus->subordinate = max;
901 buses = (buses & 0xff00ffff) |
902 ((unsigned int) (bus->subordinate) << 16);
903 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
904 pci_write_config16(dev, PCI_COMMAND, cr);
906 printk_spew("%s returns max %d\n", __func__, max);
911 Tell the EISA int controller this int must be level triggered
912 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
914 static void pci_level_irq(unsigned char intNum)
916 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
918 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
919 intBits |= (1 << intNum);
921 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
924 outb((unsigned char) intBits, 0x4d0);
925 outb((unsigned char) (intBits >> 8), 0x4d1);
927 /* this seems like an error but is not ... */
929 if (inb(0x4d0) != (intBits & 0xf)) {
930 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
931 __func__, intBits &0xf, inb(0x4d0));
933 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
934 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
935 __func__, (intBits>>8) &0xf, inb(0x4d1));
941 This function assigns IRQs for all functions contained within
942 the indicated device address. If the device does not exist or does
943 not require interrupts then this function has no effect.
945 This function should be called for each PCI slot in your system.
947 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
949 The particular irq #s that are passed in depend on the routing inside
950 your southbridge and on your motherboard.
954 void pci_assign_irqs(unsigned bus, unsigned slot,
955 const unsigned char pIntAtoD[4])
961 unsigned char readback;
963 /* Each slot may contain up to eight functions */
964 for (functNum = 0; functNum < 8; functNum++) {
965 pdev = dev_find_slot(bus, (slot << 3) + functNum);
968 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
970 // PCI spec says all other values are reserved
971 if ((line >= 1) && (line <= 4)) {
972 irq = pIntAtoD[line - 1];
974 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
975 irq, bus, slot, functNum);
977 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
980 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
981 printk_debug(" Readback = %d\n", readback);
983 // Change to level triggered
984 pci_level_irq(pIntAtoD[line - 1]);