2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
36 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
37 #include <device/hypertransport.h>
39 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
40 #include <device/pcix.h>
42 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
43 #include <device/pciexp.h>
45 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
46 #include <device/agp.h>
48 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
49 #include <device/cardbus.h>
51 #define CONFIG_PC80_SYSTEM 1
52 #if CONFIG_PC80_SYSTEM == 1
53 #include <pc80/i8259.h>
56 u8 pci_moving_config8(struct device *dev, unsigned int reg)
58 u8 value, ones, zeroes;
59 value = pci_read_config8(dev, reg);
61 pci_write_config8(dev, reg, 0xff);
62 ones = pci_read_config8(dev, reg);
64 pci_write_config8(dev, reg, 0x00);
65 zeroes = pci_read_config8(dev, reg);
67 pci_write_config8(dev, reg, value);
72 u16 pci_moving_config16(struct device * dev, unsigned int reg)
74 u16 value, ones, zeroes;
75 value = pci_read_config16(dev, reg);
77 pci_write_config16(dev, reg, 0xffff);
78 ones = pci_read_config16(dev, reg);
80 pci_write_config16(dev, reg, 0x0000);
81 zeroes = pci_read_config16(dev, reg);
83 pci_write_config16(dev, reg, value);
88 u32 pci_moving_config32(struct device * dev, unsigned int reg)
90 u32 value, ones, zeroes;
91 value = pci_read_config32(dev, reg);
93 pci_write_config32(dev, reg, 0xffffffff);
94 ones = pci_read_config32(dev, reg);
96 pci_write_config32(dev, reg, 0x00000000);
97 zeroes = pci_read_config32(dev, reg);
99 pci_write_config32(dev, reg, value);
101 return ones ^ zeroes;
105 * Given a device, a capability type, and a last position, return the next
106 * matching capability. Always start at the head of the list.
108 * @param dev Pointer to the device structure.
109 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
110 * @param last Location of the PCI capability register to start from.
112 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
119 status = pci_read_config16(dev, PCI_STATUS);
120 if (!(status & PCI_STATUS_CAP_LIST)) {
123 switch (dev->hdr_type & 0x7f) {
124 case PCI_HEADER_TYPE_NORMAL:
125 case PCI_HEADER_TYPE_BRIDGE:
126 pos = PCI_CAPABILITY_LIST;
128 case PCI_HEADER_TYPE_CARDBUS:
129 pos = PCI_CB_CAPABILITY_LIST;
134 pos = pci_read_config8(dev, pos);
135 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
138 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
139 printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n", this_cap,
141 if (this_cap == 0xff) {
144 if (!last && (this_cap == cap)) {
150 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
156 * Given a device, and a capability type, return the next matching
157 * capability. Always start at the head of the list.
159 * @param dev Pointer to the device structure.
160 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
162 unsigned pci_find_capability(device_t dev, unsigned cap)
164 return pci_find_next_capability(dev, cap, 0);
168 * Given a device and register, read the size of the BAR for that register.
170 * @param dev Pointer to the device structure.
171 * @param index Address of the PCI configuration register.
173 struct resource *pci_get_resource(struct device *dev, unsigned long index)
175 struct resource *resource;
176 unsigned long value, attr;
177 resource_t moving, limit;
179 /* Initialize the resources to nothing. */
180 resource = new_resource(dev, index);
182 /* Get the initial value. */
183 value = pci_read_config32(dev, index);
185 /* See which bits move. */
186 moving = pci_moving_config32(dev, index);
188 /* Initialize attr to the bits that do not move. */
189 attr = value & ~moving;
191 /* If it is a 64bit resource look at the high half as well. */
192 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
193 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
194 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
195 /* Find the high bits that move. */
197 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
199 /* Find the resource constraints.
200 * Start by finding the bits that move. From there:
201 * - Size is the least significant bit of the bits that move.
202 * - Limit is all of the bits that move plus all of the lower bits.
203 * See PCI Spec 6.2.5.1.
208 resource->align = resource->gran = 0;
209 while (!(moving & resource->size)) {
210 resource->size <<= 1;
211 resource->align += 1;
214 resource->limit = limit = moving | (resource->size - 1);
217 /* Some broken hardware has read-only registers that do not
218 * really size correctly.
219 * Example: the Acer M7229 has BARs 1-4 normally read-only.
220 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
221 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
222 * violation of the spec.
223 * We catch this case and ignore it by observing which bits move,
224 * This also catches the common case unimplemented registers
225 * that always read back as 0.
229 printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
230 dev_path(dev), index, value);
233 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
234 /* An I/O mapped base address. */
235 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
236 resource->flags |= IORESOURCE_IO;
237 /* I don't want to deal with 32bit I/O resources. */
238 resource->limit = 0xffff;
240 /* A Memory mapped base address. */
241 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
242 resource->flags |= IORESOURCE_MEM;
243 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
244 resource->flags |= IORESOURCE_PREFETCH;
246 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
247 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
249 resource->limit = 0xffffffffUL;
250 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
252 resource->limit = 0x000fffffUL;
253 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
255 resource->limit = 0xffffffffffffffffULL;
256 resource->flags |= IORESOURCE_PCI64;
259 printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
260 printk(BIOS_ERR, " on dev %s at index %02lx\n",
261 dev_path(dev), index);
265 /* Don't let the limit exceed which bits can move. */
266 if (resource->limit > limit) {
267 resource->limit = limit;
274 * Given a device and an index, read the size of the BAR for that register.
276 * @param dev Pointer to the device structure.
277 * @param index Address of the PCI configuration register.
279 static void pci_get_rom_resource(struct device *dev, unsigned long index)
281 struct resource *resource;
285 /* Initialize the resources to nothing. */
286 resource = new_resource(dev, index);
288 /* Get the initial value. */
289 value = pci_read_config32(dev, index);
291 /* See which bits move. */
292 moving = pci_moving_config32(dev, index);
294 /* Clear the Enable bit. */
295 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
297 /* Find the resource constraints.
298 * Start by finding the bits that move. From there:
299 * - Size is the least significant bit of the bits that move.
300 * - Limit is all of the bits that move plus all of the lower bits.
301 * See PCI Spec 6.2.5.1.
305 resource->align = resource->gran = 0;
306 while (!(moving & resource->size)) {
307 resource->size <<= 1;
308 resource->align += 1;
311 resource->limit = moving | (resource->size - 1);
312 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
315 printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n",
316 dev_path(dev), index, value);
320 compact_resources(dev);
324 * Read the base address registers for a given device.
326 * @param dev Pointer to the dev structure.
327 * @param howmany How many registers to read (6 for device, 2 for bridge).
329 static void pci_read_bases(struct device *dev, unsigned int howmany)
333 for (index = PCI_BASE_ADDRESS_0;
334 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
335 struct resource *resource;
336 resource = pci_get_resource(dev, index);
337 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
340 compact_resources(dev);
343 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
344 unsigned index, unsigned long type)
346 /* Initialize the constraints on the current bus. */
347 struct resource *resource;
352 resource = new_resource(dev, index);
356 while ((moving & step) == 0) {
360 resource->gran = gran;
361 resource->align = gran;
362 resource->limit = moving | (step - 1);
363 resource->flags = type | IORESOURCE_PCI_BRIDGE |
369 static void pci_bridge_read_bases(struct device *dev)
371 resource_t moving_base, moving_limit, moving;
373 /* See if the bridge I/O resources are implemented. */
374 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
376 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
378 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
380 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
382 moving = moving_base & moving_limit;
384 /* Initialize the I/O space constraints on the current bus. */
385 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
387 /* See if the bridge prefmem resources are implemented. */
389 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
391 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) <<
395 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) <<
398 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) <<
401 moving = moving_base & moving_limit;
402 /* Initialize the prefetchable memory constraints on the current bus. */
403 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
404 IORESOURCE_MEM | IORESOURCE_PREFETCH);
406 /* See if the bridge mem resources are implemented. */
407 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
408 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
410 moving = moving_base & moving_limit;
412 /* Initialize the memory resources on the current bus. */
413 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
416 compact_resources(dev);
419 void pci_dev_read_resources(struct device *dev)
421 pci_read_bases(dev, 6);
422 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
425 void pci_bus_read_resources(struct device *dev)
427 pci_bridge_read_bases(dev);
428 pci_read_bases(dev, 2);
429 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
432 void pci_domain_read_resources(struct device *dev)
434 struct resource *res;
436 /* Initialize the system-wide I/O space constraints. */
437 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
438 res->limit = 0xffffUL;
439 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
442 /* Initialize the system-wide memory resources constraints. */
443 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
444 res->limit = 0xffffffffULL;
445 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
449 static void pci_set_resource(struct device *dev, struct resource *resource)
451 resource_t base, end;
453 /* Make certain the resource has actually been assigned a value. */
454 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
455 printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
456 dev_path(dev), resource->index,
457 resource_type(resource), resource->size);
461 /* If this resource is fixed don't worry about it. */
462 if (resource->flags & IORESOURCE_FIXED) {
466 /* If I have already stored this resource don't worry about it. */
467 if (resource->flags & IORESOURCE_STORED) {
471 /* If the resource is subtractive don't worry about it. */
472 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
476 /* Only handle PCI memory and I/O resources for now. */
477 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
480 /* Enable the resources in the command register. */
481 if (resource->size) {
482 if (resource->flags & IORESOURCE_MEM) {
483 dev->command |= PCI_COMMAND_MEMORY;
485 if (resource->flags & IORESOURCE_IO) {
486 dev->command |= PCI_COMMAND_IO;
488 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
489 dev->command |= PCI_COMMAND_MASTER;
492 /* Get the base address. */
493 base = resource->base;
496 end = resource_end(resource);
498 /* Now store the resource. */
499 resource->flags |= IORESOURCE_STORED;
501 /* PCI Bridges have no enable bit. They are disabled if the base of
502 * the range is greater than the limit. If the size is zero, disable
503 * by setting the base = limit and end = limit - 2^gran.
505 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
506 base = resource->limit;
507 end = resource->limit - (1 << resource->gran);
508 resource->base = base;
511 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
512 unsigned long base_lo, base_hi;
513 /* Some chipsets allow us to set/clear the I/O bit
514 * (e.g. VIA 82c686a). So set it to be safe.
516 base_lo = base & 0xffffffff;
517 base_hi = (base >> 32) & 0xffffffff;
518 if (resource->flags & IORESOURCE_IO) {
519 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
521 pci_write_config32(dev, resource->index, base_lo);
522 if (resource->flags & IORESOURCE_PCI64) {
523 pci_write_config32(dev, resource->index + 4, base_hi);
525 } else if (resource->index == PCI_IO_BASE) {
526 /* Set the I/O ranges. */
527 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
528 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
529 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
530 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
531 } else if (resource->index == PCI_MEMORY_BASE) {
532 /* Set the memory range. */
533 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
534 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
535 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
536 /* Set the prefetchable memory range. */
537 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
538 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
539 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
540 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
542 /* Don't let me think I stored the resource. */
543 resource->flags &= ~IORESOURCE_STORED;
544 printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
547 report_resource_stored(dev, resource, "");
551 void pci_dev_set_resources(struct device *dev)
553 struct resource *res;
557 for (res = dev->resource_list; res; res = res->next) {
558 pci_set_resource(dev, res);
560 for (link = 0; link < dev->links; link++) {
562 bus = &dev->link[link];
564 assign_resources(bus);
568 /* Set a default latency timer. */
569 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
571 /* Set a default secondary latency timer. */
572 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
573 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
576 /* Zero the IRQ settings. */
577 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
579 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
581 /* Set the cache line size, so far 64 bytes is good for everyone. */
582 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
585 void pci_dev_enable_resources(struct device *dev)
587 const struct pci_operations *ops;
590 /* Set the subsystem vendor and device id for mainboard devices. */
592 if (dev->on_mainboard && ops && ops->set_subsystem) {
593 printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
595 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
596 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
597 ops->set_subsystem(dev,
598 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
599 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
601 command = pci_read_config16(dev, PCI_COMMAND);
602 command |= dev->command;
604 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
606 printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
607 pci_write_config16(dev, PCI_COMMAND, command);
610 void pci_bus_enable_resources(struct device *dev)
614 /* Enable I/O in command register if there is VGA card
615 * connected with (even it does not claim I/O resource).
617 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
618 dev->command |= PCI_COMMAND_IO;
619 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
620 ctrl |= dev->link[0].bridge_ctrl;
621 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
622 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
623 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
625 pci_dev_enable_resources(dev);
626 enable_childrens_resources(dev);
629 void pci_bus_reset(struct bus *bus)
632 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
633 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
634 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
636 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
637 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
641 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
643 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
644 ((device & 0xffff) << 16) | (vendor & 0xffff));
647 /** default handler: only runs the relevant pci bios. */
648 void pci_dev_init(struct device *dev)
650 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
651 struct rom_header *rom, *ram;
653 if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
654 ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
657 if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
658 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
661 rom = pci_rom_probe(dev);
665 ram = pci_rom_load(dev, rom);
669 run_bios(dev, (unsigned long)ram);
671 #if CONFIG_CONSOLE_VGA == 1
672 if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA)
674 #endif /* CONFIG_CONSOLE_VGA */
675 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
678 /** Default device operation for PCI devices */
679 static struct pci_operations pci_dev_ops_pci = {
680 .set_subsystem = pci_dev_set_subsystem,
683 struct device_operations default_pci_ops_dev = {
684 .read_resources = pci_dev_read_resources,
685 .set_resources = pci_dev_set_resources,
686 .enable_resources = pci_dev_enable_resources,
687 .init = pci_dev_init,
690 .ops_pci = &pci_dev_ops_pci,
693 /** Default device operations for PCI bridges */
694 static struct pci_operations pci_bus_ops_pci = {
698 struct device_operations default_pci_ops_bus = {
699 .read_resources = pci_bus_read_resources,
700 .set_resources = pci_dev_set_resources,
701 .enable_resources = pci_bus_enable_resources,
703 .scan_bus = pci_scan_bridge,
705 .reset_bus = pci_bus_reset,
706 .ops_pci = &pci_bus_ops_pci,
710 * @brief Detect the type of downstream bridge
712 * This function is a heuristic to detect which type of bus is downstream
713 * of a PCI-to-PCI bridge. This functions by looking for various capability
714 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
715 * Hypertransport all seem to have appropriate capabilities.
717 * When only a PCI-Express capability is found the type
718 * is examined to see which type of bridge we have.
720 * @param dev Pointer to the device structure of the bridge.
721 * @return Appropriate bridge operations.
723 static struct device_operations *get_pci_bridge_ops(device_t dev)
727 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
728 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
730 printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
731 return &default_pcix_ops_bus;
734 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
735 /* How do I detect an PCI to AGP bridge? */
737 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
739 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
741 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
742 if ((flags >> 13) == 1) {
743 /* Host or Secondary Interface */
744 printk(BIOS_DEBUG, "%s subordinate bus Hypertransport\n",
746 return &default_ht_ops_bus;
750 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
751 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
754 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
755 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
756 case PCI_EXP_TYPE_ROOT_PORT:
757 case PCI_EXP_TYPE_UPSTREAM:
758 case PCI_EXP_TYPE_DOWNSTREAM:
759 printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
761 return &default_pciexp_ops_bus;
762 case PCI_EXP_TYPE_PCI_BRIDGE:
763 printk(BIOS_DEBUG, "%s subordinate PCI\n", dev_path(dev));
764 return &default_pci_ops_bus;
770 return &default_pci_ops_bus;
774 * Set up PCI device operation. Check if it already has a driver. If not, use
775 * find_device_operations, or set to a default based on type.
777 * @param dev Pointer to the device whose pci_ops you want to set.
780 static void set_pci_ops(struct device *dev)
782 struct pci_driver *driver;
787 /* Look through the list of setup drivers and find one for
790 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
791 if ((driver->vendor == dev->vendor) &&
792 (driver->device == dev->device)) {
793 dev->ops = (struct device_operations *)driver->ops;
794 printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
796 driver->vendor, driver->device,
797 (driver->ops->scan_bus ? "bus " : ""));
802 /* If I don't have a specific driver use the default operations */
803 switch (dev->hdr_type & 0x7f) { /* header type */
804 case PCI_HEADER_TYPE_NORMAL: /* standard header */
805 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
807 dev->ops = &default_pci_ops_dev;
809 case PCI_HEADER_TYPE_BRIDGE:
810 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
812 dev->ops = get_pci_bridge_ops(dev);
814 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
815 case PCI_HEADER_TYPE_CARDBUS:
816 dev->ops = &default_cardbus_ops_bus;
822 printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown header "
823 "type %02x, ignoring.\n",
825 dev->vendor, dev->device,
826 dev->class >> 8, dev->hdr_type);
833 * @brief See if we have already allocated a device structure for a given devfn.
835 * Given a linked list of PCI device structures and a devfn number, find the
836 * device structure correspond to the devfn, if present. This function also
837 * removes the device structure from the linked list.
839 * @param list The device structure list.
840 * @param devfn A device/function number.
842 * @return Pointer to the device structure found or NULL if we have not
843 * allocated a device for this devfn yet.
845 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
849 for (; *list; list = &(*list)->sibling) {
850 if ((*list)->path.type != DEVICE_PATH_PCI) {
851 printk(BIOS_ERR, "child %s not a pci device\n",
855 if ((*list)->path.pci.devfn == devfn) {
856 /* Unlink from the list. */
858 *list = (*list)->sibling;
864 /* Just like alloc_dev() add the device to the list of devices on the
865 * bus. When the list of devices was formed we removed all of the
866 * parents children, and now we are interleaving static and dynamic
867 * devices in order on the bus.
870 struct device *child;
871 /* Find the last child of our parent. */
872 for (child = dev->bus->children; child && child->sibling;) {
873 child = child->sibling;
875 /* Place the device on the list of children of its parent. */
877 child->sibling = dev;
879 dev->bus->children = dev;
887 * @brief Scan a PCI bus.
889 * Determine the existence of a given PCI device. Allocate a new struct device
890 * if dev==NULL was passed in and the device exists in hardware.
892 * @param bus pointer to the bus structure
893 * @param devfn to look at
895 * @return The device structure for hte device (if found)
896 * or the NULL if no device is found.
898 device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
903 /* Detect if a device is present. */
907 dummy.path.type = DEVICE_PATH_PCI;
908 dummy.path.pci.devfn = devfn;
909 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
910 /* Have we found something?
911 * Some broken boards return 0 if a slot is empty, but
912 * the expected answer is 0xffffffff
914 if (id == 0xffffffff) {
917 if ((id == 0x00000000) || (id == 0x0000ffff) ||
918 (id == 0xffff0000)) {
919 printk(BIOS_SPEW, "%s, bad id 0x%x\n", dev_path(&dummy), id);
922 dev = alloc_dev(bus, &dummy.path);
924 /* Enable/disable the device. Once we have found the device-
925 * specific operations this operations we will disable the
926 * device with those as well.
928 * This is geared toward devices that have subfunctions
929 * that do not show up by default.
931 * If a device is a stuff option on the motherboard
932 * it may be absent and enable_dev() must cope.
934 /* Run the magic enable sequence for the device. */
935 if (dev->chip_ops && dev->chip_ops->enable_dev) {
936 dev->chip_ops->enable_dev(dev);
938 /* Now read the vendor and device ID. */
939 id = pci_read_config32(dev, PCI_VENDOR_ID);
941 /* If the device does not have a PCI ID disable it. Possibly
942 * this is because we have already disabled the device. But
943 * this also handles optional devices that may not always
946 /* If the chain is fully enumerated quit */
947 if ((id == 0xffffffff) || (id == 0x00000000) ||
948 (id == 0x0000ffff) || (id == 0xffff0000)) {
950 printk(BIOS_INFO, "PCI: Static device %s not found, disabling it.\n",
957 /* Read the rest of the PCI configuration information. */
958 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
959 class = pci_read_config32(dev, PCI_CLASS_REVISION);
961 /* Store the interesting information in the device structure. */
962 dev->vendor = id & 0xffff;
963 dev->device = (id >> 16) & 0xffff;
964 dev->hdr_type = hdr_type;
966 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
967 dev->class = class >> 8;
969 /* Architectural/System devices always need to be bus masters. */
970 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
971 dev->command |= PCI_COMMAND_MASTER;
973 /* Look at the vendor and device ID, or at least the header type and
974 * class and figure out which set of configuration methods to use.
975 * Unless we already have some PCI ops.
979 /* Now run the magic enable/disable sequence for the device. */
980 if (dev->ops && dev->ops->enable) {
981 dev->ops->enable(dev);
984 /* Display the device. */
985 printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n",
987 dev->vendor, dev->device,
988 dev->enabled ? "enabled" : "disabled",
989 dev->ops ? "" : " No operations");
995 * @brief Scan a PCI bus.
997 * Determine the existence of devices and bridges on a PCI bus. If there are
998 * bridges on the bus, recursively scan the buses behind the bridges.
1000 * This function is the default scan_bus() method for the root device
1003 * @param bus pointer to the bus structure
1004 * @param min_devfn minimum devfn to look at in the scan usually 0x00
1005 * @param max_devfn maximum devfn to look at in the scan usually 0xff
1006 * @param max current bus number
1008 * @return The maximum bus number found, after scanning all subordinate busses
1010 unsigned int pci_scan_bus(struct bus *bus,
1011 unsigned min_devfn, unsigned max_devfn,
1015 struct device *old_devices;
1016 struct device *child;
1018 #if CONFIG_PCI_BUS_SEGN_BITS
1019 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
1020 bus->secondary >> 8, bus->secondary & 0xff);
1022 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1025 old_devices = bus->children;
1026 bus->children = NULL;
1029 /* Probe all devices/functions on this bus with some optimization for
1030 * non-existence and single function devices.
1032 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1035 /* First thing setup the device structure */
1036 dev = pci_scan_get_dev(&old_devices, devfn);
1038 /* See if a device is present and setup the device structure. */
1039 dev = pci_probe_dev(dev, bus, devfn);
1041 /* If this is not a multi function device, or the device is
1042 * not present don't waste time probing another function.
1043 * Skip to next device.
1045 if ((PCI_FUNC(devfn) == 0x00) &&
1047 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1053 /* Warn if any leftover static devices are are found.
1054 * There's probably a problem in the Config.lb.
1058 printk(BIOS_WARNING, "PCI: Left over static devices:\n");
1059 for (left = old_devices; left; left = left->sibling) {
1060 printk(BIOS_WARNING, "%s\n", dev_path(left));
1062 printk(BIOS_WARNING, "PCI: Check your mainboard Config.lb.\n");
1065 /* For all children that implement scan_bus() (i.e. bridges)
1066 * scan the bus behind that child.
1068 for (child = bus->children; child; child = child->sibling) {
1069 max = scan_bus(child, max);
1072 /* We've scanned the bus and so we know all about what's on the other
1073 * side of any bridges that may be on this bus plus any devices.
1074 * Return how far we've got finding sub-buses.
1076 printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
1082 * @brief Scan a PCI bridge and the buses behind the bridge.
1084 * Determine the existence of buses behind the bridge. Set up the bridge
1085 * according to the result of the scan.
1087 * This function is the default scan_bus() method for PCI bridge devices.
1089 * @param dev Pointer to the bridge device.
1090 * @param max The highest bus number assigned up to now.
1091 * @return The maximum bus number found, after scanning all subordinate buses.
1093 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1094 unsigned int (*do_scan_bus) (struct bus * bus,
1103 printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
1105 bus = &dev->link[0];
1109 /* Set up the primary, secondary and subordinate bus numbers. We have
1110 * no idea how many buses are behind this bridge yet, so we set the
1111 * subordinate bus number to 0xff for the moment.
1113 bus->secondary = ++max;
1114 bus->subordinate = 0xff;
1116 /* Clear all status bits and turn off memory, I/O and master enables. */
1117 cr = pci_read_config16(dev, PCI_COMMAND);
1118 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1119 pci_write_config16(dev, PCI_STATUS, 0xffff);
1121 /* Read the existing primary/secondary/subordinate bus
1122 * number configuration.
1124 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1126 /* Configure the bus numbers for this bridge: the configuration
1127 * transactions will not be propagated by the bridge if it is not
1128 * correctly configured.
1130 buses &= 0xff000000;
1131 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1132 ((unsigned int)(bus->secondary) << 8) |
1133 ((unsigned int)(bus->subordinate) << 16));
1134 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1136 /* Now we can scan all subordinate buses
1137 * i.e. the bus behind the bridge.
1139 max = do_scan_bus(bus, 0x00, 0xff, max);
1141 /* We know the number of buses behind this bridge. Set the subordinate
1142 * bus number to its real value.
1144 bus->subordinate = max;
1145 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1146 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1147 pci_write_config16(dev, PCI_COMMAND, cr);
1149 printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
1154 * @brief Scan a PCI bridge and the buses behind the bridge.
1156 * Determine the existence of buses behind the bridge. Set up the bridge
1157 * according to the result of the scan.
1159 * This function is the default scan_bus() method for PCI bridge devices.
1161 * @param dev Pointer to the bridge device.
1162 * @param max The highest bus number assigned up to now.
1163 * @return The maximum bus number found, after scanning all subordinate buses.
1165 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1167 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1171 * @brief Scan a PCI domain.
1173 * This function is the default scan_bus() method for PCI domains.
1175 * @param dev pointer to the domain
1176 * @param max the highest bus number assgined up to now
1178 * @return The maximum bus number found, after scanning all subordinate busses
1180 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1182 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
1186 #if CONFIG_PC80_SYSTEM == 1
1189 * @brief Assign IRQ numbers
1191 * This function assigns IRQs for all functions contained within the indicated
1192 * device address. If the device does not exist or does not require interrupts
1193 * then this function has no effect.
1195 * This function should be called for each PCI slot in your system.
1199 * @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through
1200 * PINTD of this slot. The particular irq #s that are passed in
1201 * depend on the routing inside your southbridge and on your
1204 void pci_assign_irqs(unsigned bus, unsigned slot,
1205 const unsigned char pIntAtoD[4])
1212 /* Each slot may contain up to eight functions */
1213 for (funct = 0; funct < 8; funct++) {
1214 pdev = dev_find_slot(bus, (slot << 3) + funct);
1219 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1221 // PCI spec says all values except 1..4 are reserved.
1222 if ((line < 1) || (line > 4))
1225 irq = pIntAtoD[line - 1];
1227 printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
1228 irq, bus, slot, funct);
1230 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1231 pIntAtoD[line - 1]);
1233 #ifdef PARANOID_IRQ_ASSIGNMENTS
1234 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1235 printk(BIOS_DEBUG, " Readback = %d\n", irq);
1238 // Change to level triggered
1239 i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED);