2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
35 #include <part/hard_reset.h>
36 #include <part/fallback_boot.h>
38 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
39 #include <device/hypertransport.h>
41 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
42 #include <device/pcix.h>
44 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
45 #include <device/pciexp.h>
47 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
48 #include <device/agp.h>
50 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
51 #include <device/cardbus.h>
54 uint8_t pci_moving_config8(struct device *dev, unsigned reg)
56 uint8_t value, ones, zeroes;
57 value = pci_read_config8(dev, reg);
59 pci_write_config8(dev, reg, 0xff);
60 ones = pci_read_config8(dev, reg);
62 pci_write_config8(dev, reg, 0x00);
63 zeroes = pci_read_config8(dev, reg);
65 pci_write_config8(dev, reg, value);
70 uint16_t pci_moving_config16(struct device *dev, unsigned reg)
72 uint16_t value, ones, zeroes;
73 value = pci_read_config16(dev, reg);
75 pci_write_config16(dev, reg, 0xffff);
76 ones = pci_read_config16(dev, reg);
78 pci_write_config16(dev, reg, 0x0000);
79 zeroes = pci_read_config16(dev, reg);
81 pci_write_config16(dev, reg, value);
86 uint32_t pci_moving_config32(struct device *dev, unsigned reg)
88 uint32_t value, ones, zeroes;
89 value = pci_read_config32(dev, reg);
91 pci_write_config32(dev, reg, 0xffffffff);
92 ones = pci_read_config32(dev, reg);
94 pci_write_config32(dev, reg, 0x00000000);
95 zeroes = pci_read_config32(dev, reg);
97 pci_write_config32(dev, reg, value);
102 unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last)
108 status = pci_read_config16(dev, PCI_STATUS);
109 if (!(status & PCI_STATUS_CAP_LIST)) {
112 switch(dev->hdr_type & 0x7f) {
113 case PCI_HEADER_TYPE_NORMAL:
114 case PCI_HEADER_TYPE_BRIDGE:
115 pos = PCI_CAPABILITY_LIST;
117 case PCI_HEADER_TYPE_CARDBUS:
118 pos = PCI_CB_CAPABILITY_LIST;
123 pos = pci_read_config8(dev, pos);
124 while(reps-- && (pos >= 0x40)) { /* loop through the linked list */
127 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
128 printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
129 if (this_cap == 0xff) {
132 if (!last && (this_cap == cap)) {
138 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
143 unsigned pci_find_capability(device_t dev, unsigned cap)
145 return pci_find_next_capability(dev, cap, 0);
149 /** Given a device and register, read the size of the BAR for that register.
150 * @param dev Pointer to the device structure
151 * @param resource Pointer to the resource structure
152 * @param index Address of the pci configuration register
154 struct resource *pci_get_resource(struct device *dev, unsigned long index)
156 struct resource *resource;
157 unsigned long value, attr;
158 resource_t moving, limit;
160 /* Initialize the resources to nothing */
161 resource = new_resource(dev, index);
163 /* Get the initial value */
164 value = pci_read_config32(dev, index);
166 /* See which bits move */
167 moving = pci_moving_config32(dev, index);
169 /* Initialize attr to the bits that do not move */
170 attr = value & ~moving;
172 /* If it is a 64bit resource look at the high half as well */
173 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
174 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
176 /* Find the high bits that move */
177 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
179 /* Find the resource constraints.
181 * Start by finding the bits that move. From there:
182 * - Size is the least significant bit of the bits that move.
183 * - Limit is all of the bits that move plus all of the lower bits.
184 * See PCI Spec 6.2.5.1 ...
189 resource->align = resource->gran = 0;
190 while(!(moving & resource->size)) {
191 resource->size <<= 1;
192 resource->align += 1;
195 resource->limit = limit = moving | (resource->size - 1);
198 * some broken hardware has read-only registers that do not
199 * really size correctly.
200 * Example: the acer m7229 has BARs 1-4 normally read-only.
201 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
202 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
203 * violation of the spec.
204 * We catch this case and ignore it by observing which bits move,
205 * This also catches the common case unimplemented registers
206 * that always read back as 0.
211 "%s register %02lx(%08lx), read-only ignoring it\n",
212 dev_path(dev), index, value);
216 else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
217 /* An I/O mapped base address */
218 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
219 resource->flags |= IORESOURCE_IO;
220 /* I don't want to deal with 32bit I/O resources */
221 resource->limit = 0xffff;
224 /* A Memory mapped base address */
225 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
226 resource->flags |= IORESOURCE_MEM;
227 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
228 resource->flags |= IORESOURCE_PREFETCH;
230 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
231 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
233 resource->limit = 0xffffffffUL;
235 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
237 resource->limit = 0x000fffffUL;
239 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
241 resource->limit = 0xffffffffffffffffULL;
242 resource->flags |= IORESOURCE_PCI64;
249 /* Don't let the limit exceed which bits can move */
250 if (resource->limit > limit) {
251 resource->limit = limit;
254 if (resource->flags) {
255 printk_debug("%s %02x ->",
256 dev_path(dev), resource->index);
257 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
258 value, zeroes, ones, attr);
260 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ",
263 resource->size, resource->limit,
264 resource_type(resource));
271 static void pci_get_rom_resource(struct device *dev, unsigned long index)
273 struct resource *resource;
277 if ((dev->on_mainboard) && (dev->rom_address == 0)) {
278 //skip it if rom_address is not set in MB Config.lb
282 /* Initialize the resources to nothing */
283 resource = new_resource(dev, index);
285 /* Get the initial value */
286 value = pci_read_config32(dev, index);
288 /* See which bits move */
289 moving = pci_moving_config32(dev, index);
290 /* clear the Enable bit */
291 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
293 /* Find the resource constraints.
295 * Start by finding the bits that move. From there:
296 * - Size is the least significant bit of the bits that move.
297 * - Limit is all of the bits that move plus all of the lower bits.
298 * See PCI Spec 6.2.5.1 ...
302 resource->align = resource->gran = 0;
303 while (!(moving & resource->size)) {
304 resource->size <<= 1;
305 resource->align += 1;
308 resource->limit = moving | (resource->size - 1);
313 printk_debug("%s register %02lx(%08lx), read-only ignoring it\n",
314 dev_path(dev), index, value);
318 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
321 /* for on board device with embedded ROM image, the ROM image is at
322 * fixed address specified in the Config.lb, the dev->rom_address is
323 * inited by driver_pci_onboard_ops::enable_dev() */
324 if ((dev->on_mainboard) && (dev->rom_address != 0)) {
325 resource->base = dev->rom_address;
326 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
327 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
330 compact_resources(dev);
333 /** Read the base address registers for a given device.
334 * @param dev Pointer to the dev structure
335 * @param howmany How many registers to read (6 for device, 2 for bridge)
337 static void pci_read_bases(struct device *dev, unsigned int howmany)
341 for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
342 struct resource *resource;
343 resource = pci_get_resource(dev, index);
344 index += (resource->flags & IORESOURCE_PCI64)?8:4;
347 compact_resources(dev);
350 static void pci_set_resource(struct device *dev, struct resource *resource);
352 static void pci_record_bridge_resource(
353 struct device *dev, resource_t moving,
354 unsigned index, unsigned long mask, unsigned long type)
356 /* Initiliaze the constraints on the current bus */
357 struct resource *resource;
362 resource = new_resource(dev, index);
366 while((moving & step) == 0) {
370 resource->gran = gran;
371 resource->align = gran;
372 resource->limit = moving | (step - 1);
373 resource->flags = type | IORESOURCE_PCI_BRIDGE;
374 compute_allocate_resource(&dev->link[0], resource, mask, type);
375 /* If there is nothing behind the resource,
376 * clear it and forget it.
378 if (resource->size == 0) {
379 #if CONFIG_PCI_64BIT_PREF_MEM == 1
380 resource->base = moving;
382 resource->base = moving & 0xffffffff;
384 resource->flags |= IORESOURCE_ASSIGNED;
385 resource->flags &= ~IORESOURCE_STORED;
386 pci_set_resource(dev, resource);
393 static void pci_bridge_read_bases(struct device *dev)
395 resource_t moving_base, moving_limit, moving;
397 /* See if the bridge I/O resources are implemented */
398 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
399 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
401 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
402 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
404 moving = moving_base & moving_limit;
406 /* Initialize the io space constraints on the current bus */
407 pci_record_bridge_resource(
408 dev, moving, PCI_IO_BASE,
409 IORESOURCE_IO, IORESOURCE_IO);
412 /* See if the bridge prefmem resources are implemented */
413 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
414 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
416 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
417 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
419 moving = moving_base & moving_limit;
420 /* Initiliaze the prefetchable memory constraints on the current bus */
421 pci_record_bridge_resource(
422 dev, moving, PCI_PREF_MEMORY_BASE,
423 IORESOURCE_MEM | IORESOURCE_PREFETCH,
424 IORESOURCE_MEM | IORESOURCE_PREFETCH);
427 /* See if the bridge mem resources are implemented */
428 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
429 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
431 moving = moving_base & moving_limit;
433 /* Initialize the memory resources on the current bus */
434 pci_record_bridge_resource(
435 dev, moving, PCI_MEMORY_BASE,
436 IORESOURCE_MEM | IORESOURCE_PREFETCH,
439 compact_resources(dev);
442 void pci_dev_read_resources(struct device *dev)
444 pci_read_bases(dev, 6);
445 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
448 void pci_bus_read_resources(struct device *dev)
450 pci_bridge_read_bases(dev);
451 pci_read_bases(dev, 2);
452 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
455 static void pci_set_resource(struct device *dev, struct resource *resource)
457 resource_t base, end;
459 /* Make certain the resource has actually been set */
460 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
461 printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n",
462 dev_path(dev), resource->index,
463 resource_type(resource),
468 /* If I have already stored this resource don't worry about it */
469 if (resource->flags & IORESOURCE_STORED) {
473 /* If the resources is substractive don't worry about it */
474 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
478 /* Only handle PCI memory and IO resources for now */
479 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
482 /* Enable the resources in the command register */
483 if (resource->size) {
484 if (resource->flags & IORESOURCE_MEM) {
485 dev->command |= PCI_COMMAND_MEMORY;
487 if (resource->flags & IORESOURCE_IO) {
488 dev->command |= PCI_COMMAND_IO;
490 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
491 dev->command |= PCI_COMMAND_MASTER;
494 /* Get the base address */
495 base = resource->base;
498 end = resource_end(resource);
500 /* Now store the resource */
501 resource->flags |= IORESOURCE_STORED;
502 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
503 unsigned long base_lo, base_hi;
505 * some chipsets allow us to set/clear the IO bit.
506 * (e.g. VIA 82c686a.) So set it to be safe)
508 base_lo = base & 0xffffffff;
509 base_hi = (base >> 32) & 0xffffffff;
510 if (resource->flags & IORESOURCE_IO) {
511 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
513 pci_write_config32(dev, resource->index, base_lo);
514 if (resource->flags & IORESOURCE_PCI64) {
515 pci_write_config32(dev, resource->index + 4, base_hi);
518 else if (resource->index == PCI_IO_BASE) {
519 /* set the IO ranges */
520 compute_allocate_resource(&dev->link[0], resource,
521 IORESOURCE_IO, IORESOURCE_IO);
522 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
523 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
524 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
525 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
527 else if (resource->index == PCI_MEMORY_BASE) {
528 /* set the memory range */
529 compute_allocate_resource(&dev->link[0], resource,
530 IORESOURCE_MEM | IORESOURCE_PREFETCH,
532 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
533 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
535 else if (resource->index == PCI_PREF_MEMORY_BASE) {
536 /* set the prefetchable memory range */
537 compute_allocate_resource(&dev->link[0], resource,
538 IORESOURCE_MEM | IORESOURCE_PREFETCH,
539 IORESOURCE_MEM | IORESOURCE_PREFETCH);
540 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
541 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
542 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
543 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
546 /* Don't let me think I stored the resource */
547 resource->flags &= ~IORESOURCE_STORED;
548 printk_err("ERROR: invalid resource->index %lx\n",
551 report_resource_stored(dev, resource, "");
555 void pci_dev_set_resources(struct device *dev)
557 struct resource *resource, *last;
561 last = &dev->resource[dev->resources];
563 for(resource = &dev->resource[0]; resource < last; resource++) {
564 pci_set_resource(dev, resource);
566 for(link = 0; link < dev->links; link++) {
568 bus = &dev->link[link];
570 assign_resources(bus);
574 /* set a default latency timer */
575 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
577 /* set a default secondary latency timer */
578 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
579 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
582 /* zero the irq settings */
583 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
585 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
587 /* set the cache line size, so far 64 bytes is good for everyone */
588 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
591 void pci_dev_enable_resources(struct device *dev)
593 const struct pci_operations *ops;
596 /* Set the subsystem vendor and device id for mainboard devices */
598 if (dev->on_mainboard && ops && ops->set_subsystem) {
599 printk_debug("%s subsystem <- %02x/%02x\n",
601 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
602 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
603 ops->set_subsystem(dev,
604 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
605 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
607 command = pci_read_config16(dev, PCI_COMMAND);
608 command |= dev->command;
609 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
610 pci_write_config16(dev, PCI_COMMAND, command);
613 void pci_bus_enable_resources(struct device *dev)
616 /* enable IO in command register if there is VGA card
617 * connected with (even it does not claim IO resource) */
618 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
619 dev->command |= PCI_COMMAND_IO;
620 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
621 ctrl |= dev->link[0].bridge_ctrl;
622 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
623 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
624 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
626 pci_dev_enable_resources(dev);
628 enable_childrens_resources(dev);
631 void pci_bus_reset(struct bus *bus)
634 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
635 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
636 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
638 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
639 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
643 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
645 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
646 ((device & 0xffff) << 16) | (vendor & 0xffff));
649 /** default handler: only runs the relevant pci bios. */
650 void pci_dev_init(struct device *dev)
652 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
653 void run_bios(struct device * dev, unsigned long addr);
654 struct rom_header *rom, *ram;
656 #if CONFIG_PCI_ROM_RUN != 1
657 /* We want to execute VGA option ROMs when CONFIG_VGA_ROM_RUN
658 * is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
659 * all other option ROM types.
661 if ((dev->class>>8)!=PCI_CLASS_DISPLAY_VGA)
665 rom = pci_rom_probe(dev);
669 ram = pci_rom_load(dev, rom);
673 run_bios(dev, (unsigned long)ram);
675 #if CONFIG_CONSOLE_VGA == 1
676 /* vga_inited is a trigger of the VGA console code. */
677 if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA) {
678 extern int vga_inited;
681 #endif /* CONFIG_CONSOLE_VGA */
682 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
685 /** Default device operation for PCI devices */
686 static struct pci_operations pci_dev_ops_pci = {
687 .set_subsystem = pci_dev_set_subsystem,
690 struct device_operations default_pci_ops_dev = {
691 .read_resources = pci_dev_read_resources,
692 .set_resources = pci_dev_set_resources,
693 .enable_resources = pci_dev_enable_resources,
694 .init = pci_dev_init,
697 .ops_pci = &pci_dev_ops_pci,
700 /** Default device operations for PCI bridges */
701 static struct pci_operations pci_bus_ops_pci = {
705 struct device_operations default_pci_ops_bus = {
706 .read_resources = pci_bus_read_resources,
707 .set_resources = pci_dev_set_resources,
708 .enable_resources = pci_bus_enable_resources,
710 .scan_bus = pci_scan_bridge,
712 .reset_bus = pci_bus_reset,
713 .ops_pci = &pci_bus_ops_pci,
717 * @brief Detect the type of downstream bridge
719 * This function is a heuristic to detect which type
720 * of bus is downstream of a pci to pci bridge. This
721 * functions by looking for various capability blocks
722 * to figure out the type of downstream bridge. PCI-X
723 * PCI-E, and Hypertransport all seem to have appropriate
726 * When only a PCI-Express capability is found the type
727 * is examined to see which type of bridge we have.
731 * @return appropriate bridge operations
733 static struct device_operations *get_pci_bridge_ops(device_t dev)
737 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
738 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
740 printk_debug("%s subbordinate bus PCI-X\n", dev_path(dev));
741 return &default_pcix_ops_bus;
744 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
745 /* How do I detect an PCI to AGP bridge? */
747 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
749 while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
751 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
752 if ((flags >> 13) == 1) {
753 /* Host or Secondary Interface */
754 printk_debug("%s subbordinate bus Hypertransport\n",
756 return &default_ht_ops_bus;
760 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
761 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
764 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
765 switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
766 case PCI_EXP_TYPE_ROOT_PORT:
767 case PCI_EXP_TYPE_UPSTREAM:
768 case PCI_EXP_TYPE_DOWNSTREAM:
769 printk_debug("%s subbordinate bus PCI Express\n",
771 return &default_pciexp_ops_bus;
772 case PCI_EXP_TYPE_PCI_BRIDGE:
773 printk_debug("%s subbordinate PCI\n",
775 return &default_pci_ops_bus;
781 return &default_pci_ops_bus;
785 * @brief Set up PCI device operation
792 static void set_pci_ops(struct device *dev)
794 struct pci_driver *driver;
799 /* Look through the list of setup drivers and find one for
802 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
803 if ((driver->vendor == dev->vendor) &&
804 (driver->device == dev->device))
806 dev->ops = driver->ops;
807 printk_spew("%s [%04x/%04x] %sops\n",
809 driver->vendor, driver->device,
810 (driver->ops->scan_bus?"bus ":""));
815 /* If I don't have a specific driver use the default operations */
816 switch(dev->hdr_type & 0x7f) { /* header type */
817 case PCI_HEADER_TYPE_NORMAL: /* standard header */
818 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
820 dev->ops = &default_pci_ops_dev;
822 case PCI_HEADER_TYPE_BRIDGE:
823 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
825 dev->ops = get_pci_bridge_ops(dev);
827 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
828 case PCI_HEADER_TYPE_CARDBUS:
829 dev->ops = &default_cardbus_ops_bus;
835 printk_err("%s [%04x/%04x/%06x] has unknown header "
836 "type %02x, ignoring.\n",
838 dev->vendor, dev->device,
839 dev->class >> 8, dev->hdr_type);
848 * @brief See if we have already allocated a device structure for a given devfn.
850 * Given a linked list of PCI device structures and a devfn number, find the
851 * device structure correspond to the devfn, if present. This function also
852 * removes the device structure from the linked list.
854 * @param list the device structure list
855 * @param devfn a device/function number
857 * @return pointer to the device structure found or null of we have not
858 * allocated a device for this devfn yet.
860 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
864 for(; *list; list = &(*list)->sibling) {
865 if ((*list)->path.type != DEVICE_PATH_PCI) {
866 printk_err("child %s not a pci device\n",
870 if ((*list)->path.pci.devfn == devfn) {
871 /* Unlink from the list */
873 *list = (*list)->sibling;
878 /* Just like alloc_dev add the device to the list of device on the bus.
879 * When the list of devices was formed we removed all of the parents
880 * children, and now we are interleaving static and dynamic devices in
885 /* Find the last child of our parent */
886 for(child = dev->bus->children; child && child->sibling; ) {
887 child = child->sibling;
889 /* Place the device on the list of children of it's parent. */
891 child->sibling = dev;
893 dev->bus->children = dev;
901 * @brief Scan a PCI bus.
903 * Determine the existence of a given PCI device.
905 * @param bus pointer to the bus structure
906 * @param devfn to look at
908 * @return The device structure for hte device (if found)
909 * or the NULL if no device is found.
911 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
916 /* Detect if a device is present */
920 dummy.path.type = DEVICE_PATH_PCI;
921 dummy.path.pci.devfn = devfn;
922 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
923 /* Have we found somthing?
924 * Some broken boards return 0 if a slot is empty.
926 if ( (id == 0xffffffff) || (id == 0x00000000) ||
927 (id == 0x0000ffff) || (id == 0xffff0000))
929 printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
932 dev = alloc_dev(bus, &dummy.path);
935 /* Enable/disable the device. Once we have
936 * found the device specific operations this
937 * operations we will disable the device with
940 * This is geared toward devices that have subfunctions
941 * that do not show up by default.
943 * If a device is a stuff option on the motherboard
944 * it may be absent and enable_dev must cope.
947 /* Run the magice enable sequence for the device */
948 if (dev->chip_ops && dev->chip_ops->enable_dev) {
949 dev->chip_ops->enable_dev(dev);
951 /* Now read the vendor and device id */
952 id = pci_read_config32(dev, PCI_VENDOR_ID);
955 /* If the device does not have a pci id disable it.
956 * Possibly this is because we have already disabled
957 * the device. But this also handles optional devices
958 * that may not always show up.
960 /* If the chain is fully enumerated quit */
961 if ( (id == 0xffffffff) || (id == 0x00000000) ||
962 (id == 0x0000ffff) || (id == 0xffff0000))
965 printk_info("Disabling static device: %s\n",
972 /* Read the rest of the pci configuration information */
973 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
974 class = pci_read_config32(dev, PCI_CLASS_REVISION);
976 /* Store the interesting information in the device structure */
977 dev->vendor = id & 0xffff;
978 dev->device = (id >> 16) & 0xffff;
979 dev->hdr_type = hdr_type;
980 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
981 dev->class = class >> 8;
984 /* Architectural/System devices always need to
987 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
988 dev->command |= PCI_COMMAND_MASTER;
990 /* Look at the vendor and device id, or at least the
991 * header type and class and figure out which set of
992 * configuration methods to use. Unless we already
997 /* Now run the magic enable/disable sequence for the device */
998 if (dev->ops && dev->ops->enable) {
999 dev->ops->enable(dev);
1003 /* Display the device and error if we don't have some pci operations
1006 printk_debug("%s [%04x/%04x] %s%s\n",
1008 dev->vendor, dev->device,
1009 dev->enabled?"enabled": "disabled",
1010 dev->ops?"" : " No operations"
1017 * @brief Scan a PCI bus.
1019 * Determine the existence of devices and bridges on a PCI bus. If there are
1020 * bridges on the bus, recursively scan the buses behind the bridges.
1022 * This function is the default scan_bus() method for the root device
1025 * @param bus pointer to the bus structure
1026 * @param min_devfn minimum devfn to look at in the scan usually 0x00
1027 * @param max_devfn maximum devfn to look at in the scan usually 0xff
1028 * @param max current bus number
1030 * @return The maximum bus number found, after scanning all subordinate busses
1032 unsigned int pci_scan_bus(struct bus *bus,
1033 unsigned min_devfn, unsigned max_devfn,
1037 device_t old_devices;
1040 #if PCI_BUS_SEGN_BITS
1041 printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
1043 printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1046 old_devices = bus->children;
1050 /* probe all devices/functions on this bus with some optimization for
1051 * non-existence and single funcion devices
1053 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1056 /* First thing setup the device structure */
1057 dev = pci_scan_get_dev(&old_devices, devfn);
1059 /* See if a device is present and setup the device
1062 dev = pci_probe_dev(dev, bus, devfn);
1064 /* if this is not a multi function device,
1065 * or the device is not present don't waste
1066 * time probing another function.
1067 * Skip to next device.
1069 if ((PCI_FUNC(devfn) == 0x00) &&
1070 (!dev || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80))))
1077 /* Die if any left over static devices are are found.
1078 * There's probably a problem in the Config.lb.
1082 for(left = old_devices; left; left = left->sibling) {
1083 printk_err("%s\n", dev_path(left));
1085 printk_warning("PCI: Left over static devices. Check your mainboard Config.lb\n");
1088 /* For all children that implement scan_bus (i.e. bridges)
1089 * scan the bus behind that child.
1091 for(child = bus->children; child; child = child->sibling) {
1092 max = scan_bus(child, max);
1096 * We've scanned the bus and so we know all about what's on
1097 * the other side of any bridges that may be on this bus plus
1100 * Return how far we've got finding sub-buses.
1102 printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
1109 * @brief Scan a PCI bridge and the buses behind the bridge.
1111 * Determine the existence of buses behind the bridge. Set up the bridge
1112 * according to the result of the scan.
1114 * This function is the default scan_bus() method for PCI bridge devices.
1116 * @param dev pointer to the bridge device
1117 * @param max the highest bus number assgined up to now
1119 * @return The maximum bus number found, after scanning all subordinate busses
1121 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1122 unsigned int (*do_scan_bus)(struct bus *bus,
1123 unsigned min_devfn, unsigned max_devfn, unsigned int max))
1129 printk_spew("%s for %s\n", __func__, dev_path(dev));
1131 bus = &dev->link[0];
1135 /* Set up the primary, secondary and subordinate bus numbers. We have
1136 * no idea how many buses are behind this bridge yet, so we set the
1137 * subordinate bus number to 0xff for the moment.
1139 bus->secondary = ++max;
1140 bus->subordinate = 0xff;
1142 /* Clear all status bits and turn off memory, I/O and master enables. */
1143 cr = pci_read_config16(dev, PCI_COMMAND);
1144 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1145 pci_write_config16(dev, PCI_STATUS, 0xffff);
1148 * Read the existing primary/secondary/subordinate bus
1149 * number configuration.
1151 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1153 /* Configure the bus numbers for this bridge: the configuration
1154 * transactions will not be propagated by the bridge if it is not
1155 * correctly configured.
1157 buses &= 0xff000000;
1158 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
1159 ((unsigned int) (bus->secondary) << 8) |
1160 ((unsigned int) (bus->subordinate) << 16));
1161 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1163 /* Now we can scan all subordinate buses
1164 * i.e. the bus behind the bridge.
1166 max = do_scan_bus(bus, 0x00, 0xff, max);
1168 /* We know the number of buses behind this bridge. Set the subordinate
1169 * bus number to its real value.
1171 bus->subordinate = max;
1172 buses = (buses & 0xff00ffff) |
1173 ((unsigned int) (bus->subordinate) << 16);
1174 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1175 pci_write_config16(dev, PCI_COMMAND, cr);
1177 printk_spew("%s returns max %d\n", __func__, max);
1182 * @brief Scan a PCI bridge and the buses behind the bridge.
1184 * Determine the existence of buses behind the bridge. Set up the bridge
1185 * according to the result of the scan.
1187 * This function is the default scan_bus() method for PCI bridge devices.
1189 * @param dev pointer to the bridge device
1190 * @param max the highest bus number assgined up to now
1192 * @return The maximum bus number found, after scanning all subordinate busses
1194 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1196 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1200 Tell the EISA int controller this int must be level triggered
1201 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
1203 void pci_level_irq(unsigned char intNum)
1205 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
1207 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
1208 intBits |= (1 << intNum);
1210 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
1213 outb((unsigned char) intBits, 0x4d0);
1214 outb((unsigned char) (intBits >> 8), 0x4d1);
1216 /* this seems like an error but is not ... */
1218 if (inb(0x4d0) != (intBits & 0xff)) {
1219 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1220 __func__, intBits &0xff, inb(0x4d0));
1222 if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
1223 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1224 __func__, (intBits>>8) &0xff, inb(0x4d1));
1230 This function assigns IRQs for all functions contained within
1231 the indicated device address. If the device does not exist or does
1232 not require interrupts then this function has no effect.
1234 This function should be called for each PCI slot in your system.
1236 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1238 The particular irq #s that are passed in depend on the routing inside
1239 your southbridge and on your motherboard.
1243 void pci_assign_irqs(unsigned bus, unsigned slot,
1244 const unsigned char pIntAtoD[4])
1250 unsigned char readback;
1252 /* Each slot may contain up to eight functions */
1253 for (functNum = 0; functNum < 8; functNum++) {
1254 pdev = dev_find_slot(bus, (slot << 3) + functNum);
1257 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1259 // PCI spec says all other values are reserved
1260 if ((line >= 1) && (line <= 4)) {
1261 irq = pIntAtoD[line - 1];
1263 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1264 irq, bus, slot, functNum);
1266 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1267 pIntAtoD[line - 1]);
1269 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1270 printk_debug(" Readback = %d\n", readback);
1272 // Change to level triggered
1273 pci_level_irq(pIntAtoD[line - 1]);