2 * This file is part of the coreboot project.
4 * Copyright (C) 2003-2004 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 David Hendricks <sc@flagen.com>
7 * Copyright (C) 2004 Li-Ta Lo <ollie@lanl.gov>
8 * Copyright (C) 2005-2006 Tyan
9 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
10 * Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #include <console/console.h>
28 #include <device/device.h>
29 #include <device/path.h>
30 #include <device/pci.h>
31 #include <device/pci_ids.h>
32 #include <device/hypertransport.h>
35 * The hypertransport link is already optimized in pre-RAM code so don't do
41 #include <cpu/amd/model_fxx_rev.h>
44 static device_t ht_scan_get_devs(device_t *old_devices)
52 * Extract the chain of devices to (first through last) for the next
53 * hypertransport device.
55 while (last && last->sibling &&
56 (last->sibling->path.type == DEVICE_PATH_PCI) &&
57 (last->sibling->path.pci.devfn > last->path.pci.devfn))
65 /* Unlink the chain from the list of old devices. */
66 *old_devices = last->sibling;
69 /* Now add the device to the list of devices on the bus. */
70 /* Find the last child of our parent. */
71 for (child = first->bus->children; child && child->sibling; )
72 child = child->sibling;
74 /* Place the chain on the list of children of their parent. */
76 child->sibling = first;
78 first->bus->children = first;
84 static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
86 /* Handle bugs in valid hypertransport frequency reporting. */
89 freq_cap = pci_read_config16(dev, pos);
90 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies. */
92 /* AMD 8131 Errata 48. */
93 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
94 (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) {
95 freq_cap &= ~(1 << HT_FREQ_800Mhz);
98 /* AMD 8151 Errata 23. */
99 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
100 (dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) {
101 freq_cap &= ~(1 << HT_FREQ_800Mhz);
104 /* AMD K8 unsupported 1GHz? */
105 if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
106 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
108 #if CONFIG_K8_REV_F_SUPPORT == 0
109 /* Only e0 later suupport 1GHz HT. */
111 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
115 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
126 unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
129 static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
132 static const u8 link_width_to_pow2[] = { 3, 4, 0, 5, 1, 2, 0, 0 };
133 static const u8 pow2_to_link_width[] = { 7, 4, 5, 0, 1, 3 };
134 unsigned present_width_cap, upstream_width_cap;
135 unsigned present_freq_cap, upstream_freq_cap;
136 unsigned ln_present_width_in, ln_upstream_width_in;
137 unsigned ln_present_width_out, ln_upstream_width_out;
138 unsigned freq, old_freq;
139 unsigned present_width, upstream_width, old_width;
141 struct ht_link cur[1];
145 /* Set the hypertransport link width and frequency. */
148 * See which side of the device our previous write to set the unitid
154 (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
156 if (!linkb_to_host) {
157 cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
158 cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
159 cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
160 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
162 cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
163 cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
164 cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
165 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
169 /* Read the capabilities. */
171 ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
173 ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
175 pci_read_config8(cur->dev, cur->pos + cur->config_off);
177 pci_read_config8(prev->dev, prev->pos + prev->config_off);
179 /* Calculate the highest useable frequency. */
180 freq = log2(present_freq_cap & upstream_freq_cap);
182 /* Calculate the highest width. */
183 ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
184 ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
185 if (ln_upstream_width_in > ln_present_width_out)
186 ln_upstream_width_in = ln_present_width_out;
187 upstream_width = pow2_to_link_width[ln_upstream_width_in];
188 present_width = pow2_to_link_width[ln_upstream_width_in] << 4;
190 ln_upstream_width_out =
191 link_width_to_pow2[(upstream_width_cap >> 4) & 7];
192 ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
193 if (ln_upstream_width_out > ln_present_width_in)
194 ln_upstream_width_out = ln_present_width_in;
195 upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
196 present_width |= pow2_to_link_width[ln_upstream_width_out];
198 /* Set the current device. */
199 old_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
201 if (freq != old_freq) {
203 pci_write_config8(cur->dev, cur->pos + cur->freq_off, freq);
205 printk(BIOS_SPEW, "HyperT FreqP old %x new %x\n",old_freq,freq);
206 new_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
208 if (new_freq != freq) {
209 printk(BIOS_ERR, "%s Hypertransport frequency would "
210 "not set. Wanted: %x, got: %x\n",
211 dev_path(dev), freq, new_freq);
214 old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
215 if (present_width != old_width) {
217 pci_write_config8(cur->dev, cur->pos + cur->config_off + 1,
220 printk(BIOS_SPEW, "HyperT widthP old %x new %x\n",
221 old_width, present_width);
222 new_width = pci_read_config8(cur->dev,
223 cur->pos + cur->config_off + 1);
224 if (new_width != present_width) {
225 printk(BIOS_ERR, "%s Hypertransport width would not "
226 "set. Wanted: %x, got: %x\n",
227 dev_path(dev), present_width, new_width);
231 /* Set the upstream device. */
232 old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
234 if (freq != old_freq) {
236 pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
238 printk(BIOS_SPEW, "HyperT freqU old %x new %x\n",
241 pci_read_config8(prev->dev, prev->pos + prev->freq_off);
243 if (new_freq != freq) {
244 printk(BIOS_ERR, "%s Hypertransport frequency would "
245 "not set. Wanted: %x, got: %x\n",
246 dev_path(prev->dev), freq, new_freq);
250 pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
251 if (upstream_width != old_width) {
253 pci_write_config8(prev->dev, prev->pos + prev->config_off + 1,
256 printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width,
258 new_width = pci_read_config8(prev->dev,
259 prev->pos + prev->config_off + 1);
260 if (new_width != upstream_width) {
261 printk(BIOS_ERR, "%s Hypertransport width would not "
262 "set. Wanted: %x, got: %x\n",
263 dev_path(prev->dev), upstream_width, new_width);
269 * Remember the current link as the previous link, but look at the
272 prev->dev = cur->dev;
273 prev->pos = cur->pos;
274 if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) {
275 prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
276 prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
277 prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
278 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
280 prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
281 prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
282 prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
283 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
289 static unsigned ht_lookup_slave_capability(struct device *dev)
295 pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos);
298 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
299 printk(BIOS_SPEW, "flags: 0x%04x\n", flags);
300 if ((flags >> 13) == 0) {
301 /* Entry is a slave secondary, success... */
310 static void ht_collapse_early_enumeration(struct bus *bus,
311 unsigned offset_unitid)
317 /* Initialize the hypertransport enumeration state. */
320 prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
321 prev.config_off = PCI_HT_CAP_HOST_WIDTH;
322 prev.freq_off = PCI_HT_CAP_HOST_FREQ;
323 prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
325 /* Wait until the link initialization is complete. */
327 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
329 /* Is this the end of the hypertransport chain? */
333 /* Has the link failed? */
334 if (ctrl & (1 << 4)) {
336 * Either the link has failed, or we have a CRC error.
337 * Sometimes this can happen due to link retrain, so
338 * lets knock it down and see if its transient.
340 ctrl |= ((1 << 4) | (1 << 8)); /* Link fail + CRC */
341 pci_write_config16(prev.dev, prev.pos + prev.ctrl_off,
343 ctrl = pci_read_config16(prev.dev,
344 prev.pos + prev.ctrl_off);
345 if (ctrl & ((1 << 4) | (1 << 8))) {
346 printk(BIOS_ALERT, "Detected error on "
347 "Hypertransport link\n");
351 } while ((ctrl & (1 << 5)) == 0);
353 /* Actually, only for one HT device HT chain, and unitid is 0. */
354 #if CONFIG_HT_CHAIN_UNITID_BASE == 0
359 /* Check if is already collapsed. */
360 if ((!offset_unitid) || (offset_unitid
361 && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0)
362 && (CONFIG_HT_CHAIN_END_UNITID_BASE
363 < CONFIG_HT_CHAIN_UNITID_BASE))))) {
369 dummy.path.type = DEVICE_PATH_PCI;
370 dummy.path.pci.devfn = PCI_DEVFN(0, 0);
372 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
373 if (!((id == 0xffffffff) || (id == 0x00000000)
374 || (id == 0x0000ffff) || (id == 0xffff0000))) {
379 /* Spin through the devices and collapse any early HT enumeration. */
380 for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
386 dummy.path.type = DEVICE_PATH_PCI;
387 dummy.path.pci.devfn = devfn;
389 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
390 if ((id == 0xffffffff) || (id == 0x00000000)
391 || (id == 0x0000ffff) || (id == 0xffff0000)) {
395 dummy.vendor = id & 0xffff;
396 dummy.device = (id >> 16) & 0xffff;
397 dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
399 pos = ht_lookup_slave_capability(&dummy);
403 /* Clear the unitid. */
404 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
406 pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
407 printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
408 dev_path(&dummy), dummy.vendor, dummy.device);
412 unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn,
413 unsigned max_devfn, unsigned int max,
414 unsigned *ht_unitid_base,
415 unsigned offset_unitid)
418 * Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this
419 * function, because of end_of_chain check. Also, we need it to
422 unsigned int next_unitid, last_unitid, min_unitid, max_unitid;
423 device_t old_devices, dev, func, last_func = 0;
427 min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
429 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
431 * Let's record the device of last HT device, so we can set the unitid
432 * to CONFIG_HT_CHAIN_END_UNITID_BASE.
434 unsigned int real_last_unitid = 0, end_used = 0;
435 u8 real_last_pos = 0;
436 device_t real_last_dev = NULL;
439 /* Restore the hypertransport chain to it's unitialized state. */
440 ht_collapse_early_enumeration(bus, offset_unitid);
442 /* See which static device nodes I have. */
443 old_devices = bus->children;
446 /* Initialize the hypertransport enumeration state. */
450 prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
451 prev.config_off = PCI_HT_CAP_HOST_WIDTH;
452 prev.freq_off = PCI_HT_CAP_HOST_FREQ;
453 prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
455 /* If present, assign unitid to a hypertransport chain. */
456 last_unitid = min_unitid -1;
457 max_unitid = next_unitid = min_unitid;
461 unsigned int count, static_count;
463 last_unitid = next_unitid;
465 /* Wait until the link initialization is complete. */
467 ctrl = pci_read_config16(prev.dev,
468 prev.pos + prev.ctrl_off);
474 if (ctrl & ((1 << 4) | (1 << 8))) {
476 * Either the link has failed, or we have a CRC
477 * error. Sometimes this can happen due to link
478 * retrain, so lets knock it down and see if
481 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + CRC
482 pci_write_config16(prev.dev,
483 prev.pos + prev.ctrl_off, ctrl);
484 ctrl = pci_read_config16(prev.dev,
485 prev.pos + prev.ctrl_off);
486 if (ctrl & ((1 << 4) | (1 << 8))) {
487 printk(BIOS_ALERT, "Detected error on "
488 "hypertransport link\n");
492 } while ((ctrl & (1 << 5)) == 0);
495 /* Get and setup the device_structure. */
496 dev = ht_scan_get_devs(&old_devices);
498 /* See if a device is present and setup the device structure. */
499 dev = pci_probe_dev(dev, bus, 0);
500 if (!dev || !dev->enabled)
503 /* Find the hypertransport link capability. */
504 pos = ht_lookup_slave_capability(dev);
506 printk(BIOS_ERR, "%s Hypertransport link capability "
507 "not found", dev_path(dev));
511 /* Update the unitid of the current device. */
512 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
515 * If the devices has a unitid set and is at devfn 0 we are
516 * done. This can happen with shadow hypertransport devices,
517 * or if we have reached the bottom of a HT device chain.
522 flags &= ~0x1f; /* Mask out base Unit ID. */
524 count = (flags >> 5) & 0x1f; /* Het unit count. */
526 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
528 /* max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7. */
529 if (next_unitid > (max_devfn >> 3)) {
532 CONFIG_HT_CHAIN_END_UNITID_BASE;
541 flags |= next_unitid & 0x1f;
542 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
544 /* Update the unitid in the device structure. */
546 for (func = dev; func; func = func->sibling) {
547 func->path.pci.devfn += (next_unitid << 3);
548 static_count = (func->path.pci.devfn >> 3)
549 - (dev->path.pci.devfn >> 3) + 1;
553 /* Compute the number of unitids consumed. */
554 printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n",
555 dev_path(dev), count, static_count);
556 if (count < static_count)
557 count = static_count;
559 /* Update the unitid of the next device. */
560 ht_unitid_base[ht_dev_num] = next_unitid;
563 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
566 real_last_unitid = next_unitid;
570 next_unitid += count;
571 if (next_unitid > max_unitid)
572 max_unitid = next_unitid;
574 /* Setup the hypetransport link. */
575 bus->reset_needed |= ht_setup_link(&prev, dev, pos);
577 printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
578 dev_path(dev), dev->vendor, dev->device,
579 (dev->enabled? "enabled" : "disabled"), next_unitid);
581 } while (last_unitid != next_unitid);
586 if (bus->reset_needed)
587 printk(BIOS_INFO, "HyperT reset needed\n");
589 printk(BIOS_DEBUG, "HyperT reset not needed\n");
592 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
593 if (offset_unitid && (ht_dev_num > 1)
594 && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE)
597 flags = pci_read_config16(real_last_dev,
598 real_last_pos + PCI_CAP_FLAGS);
600 flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
601 pci_write_config16(real_last_dev,
602 real_last_pos + PCI_CAP_FLAGS, flags);
604 for (func = real_last_dev; func; func = func->sibling) {
605 func->path.pci.devfn -= ((real_last_unitid
606 - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
610 /* Update last one. */
611 ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE;
613 printk(BIOS_DEBUG, " unitid: %04x --> %04x\n",
614 real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
617 next_unitid = max_unitid;
619 if (next_unitid > 0x20)
622 if ((bus->secondary == 0) && (next_unitid > 0x18))
623 next_unitid = 0x18; /* Avoid K8 on bus 0. */
626 * Die if any leftover static devices are are found. There's probably
627 * a problem in devicetree.cb.
631 for (left = old_devices; left; left = left->sibling)
632 printk(BIOS_DEBUG, "%s\n", dev_path(left));
634 printk(BIOS_ERR, "HT: Leftover static devices. "
635 "Check your devicetree.cb\n");
638 * Put back the leftover static device, and let pci_scan_bus()
641 if (last_func && !last_func->sibling)
642 last_func->sibling = old_devices;
645 /* Now that nothing is overlapping it is safe to scan the children. */
646 max = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, max);
651 * Scan a PCI bridge and the buses behind the bridge.
653 * Determine the existence of buses behind the bridge. Set up the bridge
654 * according to the result of the scan.
656 * This function is the default scan_bus() method for PCI bridge devices.
659 * @param min_devfn TODO
660 * @param max_devfn TODO
661 * @param max The highest bus number assgined up to now.
662 * @return The maximum bus number found, after scanning all subordinate busses.
664 static unsigned int hypertransport_scan_chain_x(struct bus *bus,
665 unsigned int min_devfn, unsigned int max_devfn, unsigned int max)
667 unsigned int ht_unitid_base[4];
668 unsigned int offset_unitid = 1;
669 return hypertransport_scan_chain(bus, min_devfn, max_devfn, max,
670 ht_unitid_base, offset_unitid);
673 unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
675 return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x);
678 /** Default device operations for hypertransport bridges */
679 static struct pci_operations ht_bus_ops_pci = {
683 struct device_operations default_ht_ops_bus = {
684 .read_resources = pci_bus_read_resources,
685 .set_resources = pci_dev_set_resources,
686 .enable_resources = pci_bus_enable_resources,
688 .scan_bus = ht_scan_bridge,
690 .reset_bus = pci_bus_reset,
691 .ops_pci = &ht_bus_ops_pci,