2 * This file is part of the coreboot project.
4 * Copyright (C) 2003-2004 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 David Hendricks <sc@flagen.com>
7 * Copyright (C) 2004 Li-Ta Lo <ollie@lanl.gov>
8 * Copyright (C) 2005-2006 Tyan
9 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
10 * Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 2005.11 yhlu add let the real sb to use small uintid
31 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/path.h>
34 #include <device/pci.h>
35 #include <device/pci_ids.h>
36 #include <device/hypertransport.h>
38 /* The hypertransport link is already optimized in pre-ram code
39 * so don't do it again
44 #include <cpu/amd/model_fxx_rev.h>
47 static device_t ht_scan_get_devs(device_t *old_devices)
52 /* Extract the chain of devices to (first through last)
53 * for the next hypertransport device.
55 while(last && last->sibling &&
56 (last->sibling->path.type == DEVICE_PATH_PCI) &&
57 (last->sibling->path.pci.devfn > last->path.pci.devfn))
63 /* Unlink the chain from the list of old devices */
64 *old_devices = last->sibling;
67 /* Now add the device to the list of devices on the bus.
69 /* Find the last child of our parent */
70 for(child = first->bus->children; child && child->sibling; ) {
71 child = child->sibling;
73 /* Place the chain on the list of children of their parent. */
75 child->sibling = first;
77 first->bus->children = first;
84 static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
86 /* Handle bugs in valid hypertransport frequency reporting */
89 freq_cap = pci_read_config16(dev, pos);
90 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
92 /* AMD 8131 Errata 48 */
93 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
94 (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) {
95 freq_cap &= ~(1 << HT_FREQ_800Mhz);
97 /* AMD 8151 Errata 23 */
98 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
99 (dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) {
100 freq_cap &= ~(1 << HT_FREQ_800Mhz);
102 /* AMD K8 Unsupported 1Ghz? */
103 if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
104 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
105 #if CONFIG_K8_REV_F_SUPPORT == 0
106 if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT
107 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
111 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
122 unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
125 static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
128 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
129 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
130 unsigned present_width_cap, upstream_width_cap;
131 unsigned present_freq_cap, upstream_freq_cap;
132 unsigned ln_present_width_in, ln_upstream_width_in;
133 unsigned ln_present_width_out, ln_upstream_width_out;
134 unsigned freq, old_freq;
135 unsigned present_width, upstream_width, old_width;
137 struct ht_link cur[1];
141 /* Set the hypertransport link width and frequency */
143 /* See which side of the device our previous write to
144 * set the unitid came from.
148 linkb_to_host = (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
149 if (!linkb_to_host) {
150 cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
151 cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
152 cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
153 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
156 cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
157 cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
158 cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
159 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
162 /* Read the capabilities */
163 present_freq_cap = ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
164 upstream_freq_cap = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
165 present_width_cap = pci_read_config8(cur->dev, cur->pos + cur->config_off);
166 upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
168 /* Calculate the highest useable frequency */
169 freq = log2(present_freq_cap & upstream_freq_cap);
171 /* Calculate the highest width */
172 ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
173 ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
174 if (ln_upstream_width_in > ln_present_width_out) {
175 ln_upstream_width_in = ln_present_width_out;
177 upstream_width = pow2_to_link_width[ln_upstream_width_in];
178 present_width = pow2_to_link_width[ln_upstream_width_in] << 4;
180 ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
181 ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
182 if (ln_upstream_width_out > ln_present_width_in) {
183 ln_upstream_width_out = ln_present_width_in;
185 upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
186 present_width |= pow2_to_link_width[ln_upstream_width_out];
188 /* Set the current device */
189 old_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
191 if (freq != old_freq) {
193 pci_write_config8(cur->dev, cur->pos + cur->freq_off, freq);
195 printk(BIOS_SPEW, "HyperT FreqP old %x new %x\n",old_freq,freq);
196 new_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
198 if (new_freq != freq) {
199 printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
200 dev_path(dev), freq, new_freq);
203 old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
204 if (present_width != old_width) {
206 pci_write_config8(cur->dev, cur->pos + cur->config_off + 1,
209 printk(BIOS_SPEW, "HyperT widthP old %x new %x\n",old_width, present_width);
210 new_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
211 if (new_width != present_width) {
212 printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
213 dev_path(dev), present_width, new_width);
217 /* Set the upstream device */
218 old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
220 if (freq != old_freq) {
222 pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
224 printk(BIOS_SPEW, "HyperT freqU old %x new %x\n", old_freq, freq);
225 new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
227 if (new_freq != freq) {
228 printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
229 dev_path(prev->dev), freq, new_freq);
232 old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
233 if (upstream_width != old_width) {
235 pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
237 printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width, upstream_width);
238 new_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
239 if (new_width != upstream_width) {
240 printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
241 dev_path(prev->dev), upstream_width, new_width);
246 /* Remember the current link as the previous link,
247 * But look at the other offsets.
249 prev->dev = cur->dev;
250 prev->pos = cur->pos;
251 if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) {
252 prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
253 prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
254 prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
255 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
257 prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
258 prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
259 prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
260 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
267 static unsigned ht_lookup_slave_capability(struct device *dev)
272 pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos);
275 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
276 printk(BIOS_SPEW, "flags: 0x%04x\n", flags);
277 if ((flags >> 13) == 0) {
278 /* Entry is a Slave secondary, success... */
286 static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_unitid)
292 /* Initialize the hypertransport enumeration state */
295 prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
296 prev.config_off = PCI_HT_CAP_HOST_WIDTH;
297 prev.freq_off = PCI_HT_CAP_HOST_FREQ;
298 prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
300 /* Wait until the link initialization is complete */
302 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
303 /* Is this the end of the hypertransport chain */
304 if (ctrl & (1 << 6)) {
307 /* Has the link failed? */
308 if (ctrl & (1 << 4)) {
310 * Either the link has failed, or we have
312 * Sometimes this can happen due to link
313 * retrain, so lets knock it down and see
316 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
317 pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
318 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
319 if (ctrl & ((1 << 4) | (1 << 8))) {
320 printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
324 } while((ctrl & (1 << 5)) == 0);
326 //actually, only for one HT device HT chain, and unitid is 0
327 #if CONFIG_HT_CHAIN_UNITID_BASE == 0
333 /* Check if is already collapsed */
334 if((!offset_unitid)|| (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
338 dummy.path.type = DEVICE_PATH_PCI;
339 dummy.path.pci.devfn = PCI_DEVFN(0, 0);
340 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
341 if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
342 (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
347 /* Spin through the devices and collapse any early
348 * hypertransport enumeration.
350 for(devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
355 dummy.path.type = DEVICE_PATH_PCI;
356 dummy.path.pci.devfn = devfn;
357 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
358 if ( (id == 0xffffffff) || (id == 0x00000000) ||
359 (id == 0x0000ffff) || (id == 0xffff0000)) {
362 dummy.vendor = id & 0xffff;
363 dummy.device = (id >> 16) & 0xffff;
364 dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
365 pos = ht_lookup_slave_capability(&dummy);
370 /* Clear the unitid */
371 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
373 pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
374 printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
375 dev_path(&dummy), dummy.vendor, dummy.device);
379 unsigned int hypertransport_scan_chain(struct bus *bus,
380 unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid)
382 //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
383 unsigned next_unitid, last_unitid;
384 device_t old_devices, dev, func;
385 unsigned min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
387 device_t last_func = 0;
391 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
392 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
393 unsigned real_last_unitid=0;
394 uint8_t real_last_pos=0;
395 device_t real_last_dev=NULL;
396 unsigned end_used = 0;
399 /* Restore the hypertransport chain to it's unitialized state */
400 ht_collapse_early_enumeration(bus, offset_unitid);
402 /* See which static device nodes I have */
403 old_devices = bus->children;
406 /* Initialize the hypertransport enumeration state */
409 prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
410 prev.config_off = PCI_HT_CAP_HOST_WIDTH;
411 prev.freq_off = PCI_HT_CAP_HOST_FREQ;
412 prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
414 /* If present assign unitid to a hypertransport chain */
415 last_unitid = min_unitid -1;
416 max_unitid = next_unitid = min_unitid;
420 unsigned count, static_count;
423 last_unitid = next_unitid;
425 /* Wait until the link initialization is complete */
427 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
430 goto end_of_chain; // End of chain
432 if (ctrl & ((1 << 4) | (1 << 8))) {
434 * Either the link has failed, or we have
436 * Sometimes this can happen due to link
437 * retrain, so lets knock it down and see
440 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
441 pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
442 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
443 if (ctrl & ((1 << 4) | (1 << 8))) {
444 printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
448 } while((ctrl & (1 << 5)) == 0);
451 /* Get and setup the device_structure */
452 dev = ht_scan_get_devs(&old_devices);
454 /* See if a device is present and setup the
457 dev = pci_probe_dev(dev, bus, 0);
458 if (!dev || !dev->enabled) {
462 /* Find the hypertransport link capability */
463 pos = ht_lookup_slave_capability(dev);
465 printk(BIOS_ERR, "%s Hypertransport link capability not found",
470 /* Update the Unitid of the current device */
471 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
473 /* If the devices has a unitid set and is at devfn 0 we are done.
474 * This can happen with shadow hypertransport devices,
475 * or if we have reached the bottom of a
476 * hypertransport device chain.
481 flags &= ~0x1f; /* mask out base Unit ID */
483 count = (flags >> 5) & 0x1f; /* get unit count */
484 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
486 if(next_unitid > (max_devfn>>3)) { // max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7
488 next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
498 flags |= next_unitid & 0x1f;
499 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
501 /* Update the Unitd id in the device structure */
503 for(func = dev; func; func = func->sibling) {
504 func->path.pci.devfn += (next_unitid << 3);
505 static_count = (func->path.pci.devfn >> 3)
506 - (dev->path.pci.devfn >> 3) + 1;
509 /* Compute the number of unitids consumed */
510 printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n",
511 dev_path(dev), count, static_count);
512 if (count < static_count) {
513 count = static_count;
516 /* Update the Unitid of the next device */
517 ht_unitid_base[ht_dev_num] = next_unitid;
520 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
523 real_last_unitid = next_unitid;
527 next_unitid += count;
528 if (next_unitid > max_unitid) {
529 max_unitid = next_unitid;
532 /* Setup the hypetransport link */
533 bus->reset_needed |= ht_setup_link(&prev, dev, pos);
535 printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
537 dev->vendor, dev->device,
538 (dev->enabled? "enabled": "disabled"), next_unitid);
540 } while (last_unitid != next_unitid);
543 if(bus->reset_needed) {
544 printk(BIOS_INFO, "HyperT reset needed\n");
547 printk(BIOS_DEBUG, "HyperT reset not needed\n");
551 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
552 if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
554 flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS);
556 flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
557 pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
559 for(func = real_last_dev; func; func = func->sibling) {
560 func->path.pci.devfn -= ((real_last_unitid - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
564 ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one
566 printk(BIOS_DEBUG, " unitid: %04x --> %04x\n",
567 real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
571 next_unitid = max_unitid;
573 if (next_unitid > 0x20) {
576 if( (bus->secondary == 0) && (next_unitid > 0x18)) {
577 next_unitid = 0x18; /* avoid K8 on bus 0 */
580 /* Die if any leftover Static devices are are found.
581 * There's probably a problem in the Config.lb.
585 for(left = old_devices; left; left = left->sibling) {
586 printk(BIOS_DEBUG, "%s\n", dev_path(left));
588 printk(BIOS_ERR, "HT: Left over static devices. Check your Config.lb\n");
589 if(last_func && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it
590 last_func->sibling = old_devices;
593 /* Now that nothing is overlapping it is safe to scan the
596 max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max);
601 * @brief Scan a PCI bridge and the buses behind the bridge.
603 * Determine the existence of buses behind the bridge. Set up the bridge
604 * according to the result of the scan.
606 * This function is the default scan_bus() method for PCI bridge devices.
608 * @param dev pointer to the bridge device
609 * @param max the highest bus number assgined up to now
611 * @return The maximum bus number found, after scanning all subordinate busses
613 static unsigned int hypertransport_scan_chain_x(struct bus *bus,
614 unsigned min_devfn, unsigned max_devfn, unsigned int max)
616 unsigned ht_unitid_base[4];
617 unsigned offset_unitid = 1;
618 return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid);
621 unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
623 return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x);
627 /** Default device operations for hypertransport bridges */
628 static struct pci_operations ht_bus_ops_pci = {
632 struct device_operations default_ht_ops_bus = {
633 .read_resources = pci_bus_read_resources,
634 .set_resources = pci_dev_set_resources,
635 .enable_resources = pci_bus_enable_resources,
637 .scan_bus = ht_scan_bridge,
639 .reset_bus = pci_bus_reset,
640 .ops_pci = &ht_bus_ops_pci,