0c1dc3959a56fb13efaec267fd95717eb1f41632
[coreboot.git] / src / devices / hypertransport.c
1 #include <bitops.h>
2 #include <console/console.h>
3 #include <device/device.h>
4 #include <device/path.h>
5 #include <device/pci.h>
6 #include <device/hypertransport.h>
7 #include <part/hard_reset.h>
8 #include <part/fallback_boot.h>
9
10 static device_t ht_scan_get_devs(device_t *old_devices)
11 {
12         device_t first, last;
13         first = *old_devices;
14         last = first;
15         while(last && last->sibling && 
16                 (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) {
17                 last = last->sibling;
18         }
19         if (first) {
20                 *old_devices = last->sibling;
21                 last->sibling = 0;
22         }
23         return first;
24 }
25
26
27 struct prev_link {
28         struct device *dev;
29         unsigned pos;
30         unsigned char config_off, freq_off, freq_cap_off;
31 };
32
33 static int ht_setup_link(struct prev_link *prev, device_t dev, unsigned pos)
34 {
35         static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
36         static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
37         unsigned present_width_cap,    upstream_width_cap;
38         unsigned present_freq_cap,     upstream_freq_cap;
39         unsigned ln_present_width_in,  ln_upstream_width_in; 
40         unsigned ln_present_width_out, ln_upstream_width_out;
41         unsigned freq, old_freq;
42         unsigned present_width, upstream_width, old_width;
43         int reset_needed;
44
45         /* Set the hypertransport link width and frequency */
46         reset_needed = 0;
47
48         /* Read the capabilities */
49         present_freq_cap   = pci_read_config16(dev, pos + PCI_HT_CAP_SLAVE_FREQ_CAP0);
50         upstream_freq_cap  = pci_read_config16(prev->dev, prev->pos + prev->freq_cap_off);
51         present_width_cap  = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0);
52         upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
53         
54         /* Calculate the highest useable frequency */
55 #if 0
56         freq = log2(present_freq_cap & upstream_freq_cap);
57 #else
58         /* Errata for 8131 - freq 5 has hardware problems don't support it */
59         freq = log2(present_freq_cap & upstream_freq_cap & 0x1f);
60 #endif
61
62         /* Calculate the highest width */
63         ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
64         ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
65         if (ln_upstream_width_in > ln_present_width_out) {
66                 ln_upstream_width_in = ln_present_width_out;
67         }
68         upstream_width = pow2_to_link_width[ln_upstream_width_in];
69         present_width  = pow2_to_link_width[ln_upstream_width_in] << 4;
70
71         ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
72         ln_present_width_in   = link_width_to_pow2[present_width_cap & 7];
73         if (ln_upstream_width_out > ln_present_width_in) {
74                 ln_upstream_width_out = ln_present_width_in;
75         }
76         upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
77         present_width  |= pow2_to_link_width[ln_upstream_width_out];
78
79         /* Set the current device */
80         old_freq = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_FREQ0);
81         if (freq != old_freq) {
82                 pci_write_config8(dev, pos + PCI_HT_CAP_SLAVE_FREQ0, freq);
83                 reset_needed = 1;
84                 printk_spew("HyperT FreqP old %x new %x\n",old_freq,freq);
85         }
86         old_width = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1);
87         if (present_width != old_width) {
88                 pci_write_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1, present_width);
89                 reset_needed = 1;
90                 printk_spew("HyperT widthP old %x new %x\n",old_width, present_width);
91         }
92
93         /* Set the upstream device */
94         old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
95         old_freq &= 0x0f;
96         if (freq != old_freq) {
97                 pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
98                 reset_needed = 1;
99                 printk_spew("HyperT freqU old %x new %x\n", old_freq, freq);
100         }
101         old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
102         if (upstream_width != old_width) {
103                 pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
104                 reset_needed = 1;
105                 printk_spew("HyperT widthU old %x new %x\n", old_width, upstream_width);
106         }
107         
108         /* Remember the current link as the previous link */
109         prev->dev = dev;
110         prev->pos = pos;
111         prev->config_off   = PCI_HT_CAP_SLAVE_WIDTH1;
112         prev->freq_off     = PCI_HT_CAP_SLAVE_FREQ1;
113         prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
114
115         return reset_needed;
116                 
117 }
118
119 static unsigned ht_lookup_slave_capability(struct device *dev)
120 {
121         unsigned pos;
122         pos = 0;
123         switch(dev->hdr_type & 0x7f) {
124         case PCI_HEADER_TYPE_NORMAL:
125         case PCI_HEADER_TYPE_BRIDGE:
126                 pos = PCI_CAPABILITY_LIST;
127                 break;
128         }
129         if (pos > PCI_CAP_LIST_NEXT) {
130                 pos = pci_read_config8(dev, pos);
131         }
132         while(pos != 0) {   /* loop through the linked list */
133                 uint8_t cap;
134                 cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
135                 printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
136                 if (cap == PCI_CAP_ID_HT) {
137                         unsigned flags;
138                         flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
139                         printk_spew("flags: 0x%04x\n", (unsigned)flags);
140                         if ((flags >> 13) == 0) {
141                                 /* Entry is a Slave secondary, success...*/
142                                 break;
143                         }
144                 }
145                 if(pos) {
146                         pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
147                 }
148         }
149         return pos;
150 }
151
152 static void ht_collapse_early_enumeration(struct bus *bus)
153 {
154         unsigned int devfn;
155
156         /* Spin through the devices and collapse any early
157          * hypertransport enumeration.
158          */
159         for(devfn = 0; devfn <= 0xff; devfn += 8) {
160                 struct device dummy;
161                 uint32_t id;
162                 unsigned pos, flags;
163                 dummy.bus              = bus;
164                 dummy.path.type        = DEVICE_PATH_PCI;
165                 dummy.path.u.pci.devfn = devfn;
166                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
167                 if (id == 0xffffffff || id == 0x00000000 || 
168                         id == 0x0000ffff || id == 0xffff0000) {
169                         continue;
170                 }
171                 dummy.vendor = id & 0xffff;
172                 dummy.device = (id >> 16) & 0xffff;
173                 dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
174                 pos = ht_lookup_slave_capability(&dummy);
175                 if (!pos){
176                         continue;
177                 }
178
179                 /* Clear the unitid */
180                 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
181                 flags &= ~0x1f;
182                 pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
183                 printk_spew("Collapsing %s [%04x/%04x]\n", 
184                         dev_path(&dummy), dummy.vendor, dummy.device);
185         }
186 }
187
188 unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max)
189 {
190         unsigned next_unitid, last_unitid, previous_unitid;
191         uint8_t previous_pos;
192         device_t old_devices, dev, func, *chain_last;
193         unsigned min_unitid = 1;
194         int reset_needed;
195         struct prev_link prev;
196
197         /* Restore the hypertransport chain to it's unitialized state */
198         ht_collapse_early_enumeration(bus);
199
200         /* See which static device nodes I have */
201         old_devices = bus->children;
202         bus->children = 0;
203         chain_last = &bus->children;
204
205         /* Initialize the hypertransport enumeration state */
206         reset_needed = 0;
207         prev.dev = bus->dev;
208         prev.pos = bus->cap;
209         prev.config_off   = PCI_HT_CAP_HOST_WIDTH;
210         prev.freq_off     = PCI_HT_CAP_HOST_FREQ;
211         prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
212         
213         /* If present assign unitid to a hypertransport chain */
214         last_unitid = min_unitid -1;
215         next_unitid = min_unitid;
216         previous_pos = 0;
217         do {
218                 uint32_t id, class;
219                 uint8_t hdr_type, pos;
220                 uint16_t flags;
221                 unsigned count, static_count;
222
223                 previous_unitid = last_unitid;
224                 last_unitid = next_unitid;
225
226                 /* Get setup the device_structure */
227                 dev = ht_scan_get_devs(&old_devices);
228
229                 if (!dev) {
230                         struct device dummy;
231                         dummy.bus              = bus;
232                         dummy.path.type        = DEVICE_PATH_PCI;
233                         dummy.path.u.pci.devfn = 0;
234                         id = pci_read_config32(&dummy, PCI_VENDOR_ID);
235                         /* If the chain is fully enumerated quit */
236                         if (id == 0xffffffff || id == 0x00000000 ||
237                                 id == 0x0000ffff || id == 0xffff0000) {
238                                 break;
239                         }
240                         dev = alloc_dev(bus, &dummy.path);
241                 }
242                 else {
243                         /* Add this device to the pci bus chain */
244                         *chain_last = dev;
245                         /* Run the magice enable/disable sequence for the device */
246                         if (dev->ops && dev->ops->enable) {
247                                 dev->ops->enable(dev);
248                         }
249                         /* Now read the vendor and device id */
250                         id = pci_read_config32(dev, PCI_VENDOR_ID);
251                 }
252                 /* Update the device chain tail */
253                 for(func = dev; func; func = func->sibling) {
254                         chain_last = &func->sibling;
255                 }
256                 
257                 /* Read the rest of the pci configuration information */
258                 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
259                 class = pci_read_config32(dev, PCI_CLASS_REVISION);
260                 
261                 /* Store the interesting information in the device structure */
262                 dev->vendor = id & 0xffff;
263                 dev->device = (id >> 16) & 0xffff;
264                 dev->hdr_type = hdr_type;
265                 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
266                 dev->class = class >> 8;
267
268                 /* Find the hypertransport link capability */
269                 pos = ht_lookup_slave_capability(dev);
270                 if (pos == 0) {
271                         printk_err("Hypertransport link capability not found");
272                         break;
273                 }
274                 
275                 /* Update the Unitid of the current device */
276                 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
277                 flags &= ~0x1f; /* mask out base Unit ID */
278                 flags |= next_unitid & 0x1f;
279                 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
280
281                 /* Update the Unitd id in the device structure */
282                 static_count = 1;
283                 for(func = dev; func; func = func->sibling) {
284                         func->path.u.pci.devfn += (next_unitid << 3);
285                         static_count = (func->path.u.pci.devfn >> 3) 
286                                 - (dev->path.u.pci.devfn >> 3) + 1;
287                 }
288
289                 /* Compute the number of unitids consumed */
290                 count = (flags >> 5) & 0x1f; /* get unit count */
291                 printk_spew("%s count: %04x static_count: %04x\n", 
292                         dev_path(dev), count, static_count);
293                 if (count < static_count) {
294                         count = static_count;
295                 }
296
297                 /* Update the Unitid of the next device */
298                 next_unitid += count;
299
300                 /* Setup the hypetransport link */
301                 reset_needed |= ht_setup_link(&prev, dev, pos);
302
303                 printk_debug("%s [%04x/%04x] %s next_unitid: %04x\n",
304                         dev_path(dev),
305                         dev->vendor, dev->device, 
306                         (dev->enable? "enabled": "disabled"), next_unitid);
307
308         } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
309 #if HAVE_HARD_RESET == 1
310         if(reset_needed) {
311                 printk_info("HyperT reset needed\n");
312                 hard_reset();
313         }
314         printk_debug("HyperT reset not needed\n");
315 #endif
316         if (next_unitid > 0x1f) {
317                 next_unitid = 0x1f;
318         }
319         return pci_scan_bus(bus, 0x00, (next_unitid << 3)|7, max);
320 }