1 /****************************************************************************
3 * Realmode X86 Emulator Library
5 * Copyright (C) 1991-2004 SciTech Software, Inc.
6 * Copyright (C) David Mosberger-Tang
7 * Copyright (C) 1999 Egbert Eich
9 * ========================================================================
11 * Permission to use, copy, modify, distribute, and sell this software and
12 * its documentation for any purpose is hereby granted without fee,
13 * provided that the above copyright notice appear in all copies and that
14 * both that copyright notice and this permission notice appear in
15 * supporting documentation, and that the name of the authors not be used
16 * in advertising or publicity pertaining to distribution of the software
17 * without specific, written prior permission. The authors makes no
18 * representations about the suitability of this software for any purpose.
19 * It is provided "as is" without express or implied warranty.
21 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
22 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
23 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
24 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
25 * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
26 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
27 * PERFORMANCE OF THIS SOFTWARE.
29 * ========================================================================
33 * Developer: Kendall Bennett
35 * Description: This file includes subroutines to implement the decoding
36 * and emulation of all the x86 extended two-byte processor
39 ****************************************************************************/
43 /*----------------------------- Implementation ----------------------------*/
45 /****************************************************************************
47 op1 - Instruction op code
50 Handles illegal opcodes.
51 ****************************************************************************/
52 void x86emuOp2_illegal_op(
56 DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
58 printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
59 M.x86.R_CS, M.x86.R_IP-2,op2);
64 #define xorl(a,b) ((a) && !(b)) || (!(a) && (b))
66 /****************************************************************************
68 Handles opcode 0x0f,0x80-0x8F
69 ****************************************************************************/
70 int x86emu_check_jump_condition(u8 op)
74 DECODE_PRINTF("JO\t");
75 return ACCESS_FLAG(F_OF);
77 DECODE_PRINTF("JNO\t");
78 return !ACCESS_FLAG(F_OF);
81 DECODE_PRINTF("JB\t");
82 return ACCESS_FLAG(F_CF);
85 DECODE_PRINTF("JNB\t");
86 return !ACCESS_FLAG(F_CF);
89 DECODE_PRINTF("JZ\t");
90 return ACCESS_FLAG(F_ZF);
93 DECODE_PRINTF("JNZ\t");
94 return !ACCESS_FLAG(F_ZF);
97 DECODE_PRINTF("JBE\t");
98 return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
101 DECODE_PRINTF("JNBE\t");
102 return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
105 DECODE_PRINTF("JS\t");
106 return ACCESS_FLAG(F_SF);
109 DECODE_PRINTF("JNS\t");
110 return !ACCESS_FLAG(F_SF);
113 DECODE_PRINTF("JP\t");
114 return ACCESS_FLAG(F_PF);
117 DECODE_PRINTF("JNP\t");
118 return !ACCESS_FLAG(F_PF);
121 DECODE_PRINTF("JL\t");
122 return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
125 DECODE_PRINTF("JNL\t");
126 return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
129 DECODE_PRINTF("JLE\t");
130 return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
134 DECODE_PRINTF("JNLE\t");
135 return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
140 void x86emuOp2_long_jump(u8 op2)
145 /* conditional jump to word offset. */
147 cond = x86emu_check_jump_condition(op2 & 0xF);
148 target = (s16) fetch_word_imm();
149 target += (s16) M.x86.R_IP;
150 DECODE_PRINTF2("%04x\n", target);
153 M.x86.R_IP = (u16)target;
154 DECODE_CLEAR_SEGOVR();
158 /****************************************************************************
160 Handles opcode 0x0f,0x90-0x9F
161 ****************************************************************************/
162 void x86emuOp2_set_byte(u8 op2)
174 cond = ACCESS_FLAG(F_OF);
178 cond = !ACCESS_FLAG(F_OF);
182 cond = ACCESS_FLAG(F_CF);
186 cond = !ACCESS_FLAG(F_CF);
190 cond = ACCESS_FLAG(F_ZF);
194 cond = !ACCESS_FLAG(F_ZF);
198 cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
202 cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
206 cond = ACCESS_FLAG(F_SF);
210 cond = !ACCESS_FLAG(F_SF);
214 cond = ACCESS_FLAG(F_PF);
218 cond = !ACCESS_FLAG(F_PF);
222 cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
226 cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
230 cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
235 cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
240 FETCH_DECODE_MODRM(mod, rh, rl);
242 destoffset = decode_rmXX_address(mod, rl);
244 store_data_byte(destoffset, cond ? 0x01 : 0x00);
245 } else { /* register to register */
246 destreg = DECODE_RM_BYTE_REGISTER(rl);
248 *destreg = cond ? 0x01 : 0x00;
250 DECODE_CLEAR_SEGOVR();
254 /****************************************************************************
256 Handles opcode 0x0f,0xa0
257 ****************************************************************************/
258 void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2))
261 DECODE_PRINTF("PUSH\tFS\n");
263 push_word(M.x86.R_FS);
264 DECODE_CLEAR_SEGOVR();
268 /****************************************************************************
270 Handles opcode 0x0f,0xa1
271 ****************************************************************************/
272 void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2))
275 DECODE_PRINTF("POP\tFS\n");
277 M.x86.R_FS = pop_word();
278 DECODE_CLEAR_SEGOVR();
282 /****************************************************************************
284 Handles opcode 0x0f,0xa3
285 ****************************************************************************/
286 void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2))
293 DECODE_PRINTF("BT\t");
294 FETCH_DECODE_MODRM(mod, rh, rl);
296 srcoffset = decode_rmXX_address(mod, rl);
297 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
302 shiftreg = DECODE_RM_LONG_REGISTER(rh);
304 bit = *shiftreg & 0x1F;
305 disp = (s16)*shiftreg >> 5;
306 srcval = fetch_data_long(srcoffset+disp);
307 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
313 shiftreg = DECODE_RM_WORD_REGISTER(rh);
315 bit = *shiftreg & 0xF;
316 disp = (s16)*shiftreg >> 4;
317 srcval = fetch_data_word(srcoffset+disp);
318 CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
320 } else { /* register to register */
321 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
322 u32 *srcreg,*shiftreg;
324 srcreg = DECODE_RM_LONG_REGISTER(rl);
326 shiftreg = DECODE_RM_LONG_REGISTER(rh);
328 bit = *shiftreg & 0x1F;
329 CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
331 u16 *srcreg,*shiftreg;
333 srcreg = DECODE_RM_WORD_REGISTER(rl);
335 shiftreg = DECODE_RM_WORD_REGISTER(rh);
337 bit = *shiftreg & 0xF;
338 CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
341 DECODE_CLEAR_SEGOVR();
345 /****************************************************************************
347 Handles opcode 0x0f,0xa4
348 ****************************************************************************/
349 void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2))
356 DECODE_PRINTF("SHLD\t");
357 FETCH_DECODE_MODRM(mod, rh, rl);
359 destoffset = decode_rmXX_address(mod, rl);
360 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
365 shiftreg = DECODE_RM_LONG_REGISTER(rh);
367 shift = fetch_byte_imm();
368 DECODE_PRINTF2("%d\n", shift);
370 destval = fetch_data_long(destoffset);
371 destval = shld_long(destval,*shiftreg,shift);
372 store_data_long(destoffset, destval);
378 shiftreg = DECODE_RM_WORD_REGISTER(rh);
380 shift = fetch_byte_imm();
381 DECODE_PRINTF2("%d\n", shift);
383 destval = fetch_data_word(destoffset);
384 destval = shld_word(destval,*shiftreg,shift);
385 store_data_word(destoffset, destval);
387 } else { /* register to register */
388 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
389 u32 *destreg,*shiftreg;
391 destreg = DECODE_RM_LONG_REGISTER(rl);
393 shiftreg = DECODE_RM_LONG_REGISTER(rh);
395 shift = fetch_byte_imm();
396 DECODE_PRINTF2("%d\n", shift);
398 *destreg = shld_long(*destreg,*shiftreg,shift);
400 u16 *destreg,*shiftreg;
402 destreg = DECODE_RM_WORD_REGISTER(rl);
404 shiftreg = DECODE_RM_WORD_REGISTER(rh);
406 shift = fetch_byte_imm();
407 DECODE_PRINTF2("%d\n", shift);
409 *destreg = shld_word(*destreg,*shiftreg,shift);
412 DECODE_CLEAR_SEGOVR();
416 /****************************************************************************
418 Handles opcode 0x0f,0xa5
419 ****************************************************************************/
420 void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2))
426 DECODE_PRINTF("SHLD\t");
427 FETCH_DECODE_MODRM(mod, rh, rl);
429 destoffset = decode_rmXX_address(mod, rl);
430 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
435 shiftreg = DECODE_RM_LONG_REGISTER(rh);
436 DECODE_PRINTF(",CL\n");
438 destval = fetch_data_long(destoffset);
439 destval = shld_long(destval,*shiftreg,M.x86.R_CL);
440 store_data_long(destoffset, destval);
446 shiftreg = DECODE_RM_WORD_REGISTER(rh);
447 DECODE_PRINTF(",CL\n");
449 destval = fetch_data_word(destoffset);
450 destval = shld_word(destval,*shiftreg,M.x86.R_CL);
451 store_data_word(destoffset, destval);
453 } else { /* register to register */
454 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
455 u32 *destreg,*shiftreg;
457 destreg = DECODE_RM_LONG_REGISTER(rl);
459 shiftreg = DECODE_RM_LONG_REGISTER(rh);
460 DECODE_PRINTF(",CL\n");
462 *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL);
464 u16 *destreg,*shiftreg;
466 destreg = DECODE_RM_WORD_REGISTER(rl);
468 shiftreg = DECODE_RM_WORD_REGISTER(rh);
469 DECODE_PRINTF(",CL\n");
471 *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL);
474 DECODE_CLEAR_SEGOVR();
478 /****************************************************************************
480 Handles opcode 0x0f,0xa8
481 ****************************************************************************/
482 void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2))
485 DECODE_PRINTF("PUSH\tGS\n");
487 push_word(M.x86.R_GS);
488 DECODE_CLEAR_SEGOVR();
492 /****************************************************************************
494 Handles opcode 0x0f,0xa9
495 ****************************************************************************/
496 void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2))
499 DECODE_PRINTF("POP\tGS\n");
501 M.x86.R_GS = pop_word();
502 DECODE_CLEAR_SEGOVR();
506 /****************************************************************************
508 Handles opcode 0x0f,0xaa
509 ****************************************************************************/
510 void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2))
517 DECODE_PRINTF("BTS\t");
518 FETCH_DECODE_MODRM(mod, rh, rl);
520 srcoffset = decode_rmXX_address(mod, rl);
521 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
526 shiftreg = DECODE_RM_LONG_REGISTER(rh);
528 bit = *shiftreg & 0x1F;
529 disp = (s16)*shiftreg >> 5;
530 srcval = fetch_data_long(srcoffset+disp);
532 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
533 store_data_long(srcoffset+disp, srcval | mask);
539 shiftreg = DECODE_RM_WORD_REGISTER(rh);
541 bit = *shiftreg & 0xF;
542 disp = (s16)*shiftreg >> 4;
543 srcval = fetch_data_word(srcoffset+disp);
544 mask = (u16)(0x1 << bit);
545 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
546 store_data_word(srcoffset+disp, srcval | mask);
548 } else { /* register to register */
549 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
550 u32 *srcreg,*shiftreg;
553 srcreg = DECODE_RM_LONG_REGISTER(rl);
555 shiftreg = DECODE_RM_LONG_REGISTER(rh);
557 bit = *shiftreg & 0x1F;
559 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
562 u16 *srcreg,*shiftreg;
565 srcreg = DECODE_RM_WORD_REGISTER(rl);
567 shiftreg = DECODE_RM_WORD_REGISTER(rh);
569 bit = *shiftreg & 0xF;
570 mask = (u16)(0x1 << bit);
571 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
575 DECODE_CLEAR_SEGOVR();
579 /****************************************************************************
581 Handles opcode 0x0f,0xac
582 ****************************************************************************/
583 void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2))
590 DECODE_PRINTF("SHLD\t");
591 FETCH_DECODE_MODRM(mod, rh, rl);
593 destoffset = decode_rmXX_address(mod, rl);
594 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
599 shiftreg = DECODE_RM_LONG_REGISTER(rh);
601 shift = fetch_byte_imm();
602 DECODE_PRINTF2("%d\n", shift);
604 destval = fetch_data_long(destoffset);
605 destval = shrd_long(destval,*shiftreg,shift);
606 store_data_long(destoffset, destval);
612 shiftreg = DECODE_RM_WORD_REGISTER(rh);
614 shift = fetch_byte_imm();
615 DECODE_PRINTF2("%d\n", shift);
617 destval = fetch_data_word(destoffset);
618 destval = shrd_word(destval,*shiftreg,shift);
619 store_data_word(destoffset, destval);
621 } else { /* register to register */
622 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
623 u32 *destreg,*shiftreg;
625 destreg = DECODE_RM_LONG_REGISTER(rl);
627 shiftreg = DECODE_RM_LONG_REGISTER(rh);
629 shift = fetch_byte_imm();
630 DECODE_PRINTF2("%d\n", shift);
632 *destreg = shrd_long(*destreg,*shiftreg,shift);
634 u16 *destreg,*shiftreg;
636 destreg = DECODE_RM_WORD_REGISTER(rl);
638 shiftreg = DECODE_RM_WORD_REGISTER(rh);
640 shift = fetch_byte_imm();
641 DECODE_PRINTF2("%d\n", shift);
643 *destreg = shrd_word(*destreg,*shiftreg,shift);
646 DECODE_CLEAR_SEGOVR();
650 /****************************************************************************
652 Handles opcode 0x0f,0xad
653 ****************************************************************************/
654 void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2))
660 DECODE_PRINTF("SHLD\t");
661 FETCH_DECODE_MODRM(mod, rh, rl);
663 destoffset = decode_rmXX_address(mod, rl);
665 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
669 shiftreg = DECODE_RM_LONG_REGISTER(rh);
670 DECODE_PRINTF(",CL\n");
672 destval = fetch_data_long(destoffset);
673 destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
674 store_data_long(destoffset, destval);
679 shiftreg = DECODE_RM_WORD_REGISTER(rh);
680 DECODE_PRINTF(",CL\n");
682 destval = fetch_data_word(destoffset);
683 destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
684 store_data_word(destoffset, destval);
686 } else { /* register to register */
687 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
688 u32 *destreg,*shiftreg;
690 destreg = DECODE_RM_LONG_REGISTER(rl);
692 shiftreg = DECODE_RM_LONG_REGISTER(rh);
693 DECODE_PRINTF(",CL\n");
695 *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL);
697 u16 *destreg,*shiftreg;
699 destreg = DECODE_RM_WORD_REGISTER(rl);
701 shiftreg = DECODE_RM_WORD_REGISTER(rh);
702 DECODE_PRINTF(",CL\n");
704 *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL);
707 DECODE_CLEAR_SEGOVR();
711 /****************************************************************************
713 Handles opcode 0x0f,0xaf
714 ****************************************************************************/
715 void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2))
721 DECODE_PRINTF("IMUL\t");
722 FETCH_DECODE_MODRM(mod, rh, rl);
724 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
729 destreg = DECODE_RM_LONG_REGISTER(rh);
731 srcoffset = decode_rmXX_address(mod, rl);
732 srcval = fetch_data_long(srcoffset);
734 imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
742 *destreg = (u32)res_lo;
748 destreg = DECODE_RM_WORD_REGISTER(rh);
750 srcoffset = decode_rmXX_address(mod, rl);
751 srcval = fetch_data_word(srcoffset);
753 res = (s16)*destreg * (s16)srcval;
763 } else { /* register to register */
764 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
765 u32 *destreg,*srcreg;
768 destreg = DECODE_RM_LONG_REGISTER(rh);
770 srcreg = DECODE_RM_LONG_REGISTER(rl);
772 imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg);
780 *destreg = (u32)res_lo;
782 u16 *destreg,*srcreg;
785 destreg = DECODE_RM_WORD_REGISTER(rh);
787 srcreg = DECODE_RM_WORD_REGISTER(rl);
788 res = (s16)*destreg * (s16)*srcreg;
799 DECODE_CLEAR_SEGOVR();
803 /****************************************************************************
805 Handles opcode 0x0f,0xb2
806 ****************************************************************************/
807 void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2))
814 DECODE_PRINTF("LSS\t");
815 FETCH_DECODE_MODRM(mod, rh, rl);
817 dstreg = DECODE_RM_WORD_REGISTER(rh);
819 srcoffset = decode_rmXX_address(mod, rl);
822 *dstreg = fetch_data_word(srcoffset);
823 M.x86.R_SS = fetch_data_word(srcoffset + 2);
824 } else { /* register to register */
828 DECODE_CLEAR_SEGOVR();
832 /****************************************************************************
834 Handles opcode 0x0f,0xb3
835 ****************************************************************************/
836 void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2))
843 DECODE_PRINTF("BTR\t");
844 FETCH_DECODE_MODRM(mod, rh, rl);
846 srcoffset = decode_rmXX_address(mod, rl);
848 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
852 shiftreg = DECODE_RM_LONG_REGISTER(rh);
854 bit = *shiftreg & 0x1F;
855 disp = (s16)*shiftreg >> 5;
856 srcval = fetch_data_long(srcoffset+disp);
858 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
859 store_data_long(srcoffset+disp, srcval & ~mask);
864 shiftreg = DECODE_RM_WORD_REGISTER(rh);
866 bit = *shiftreg & 0xF;
867 disp = (s16)*shiftreg >> 4;
868 srcval = fetch_data_word(srcoffset+disp);
869 mask = (u16)(0x1 << bit);
870 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
871 store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
873 } else { /* register to register */
874 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
875 u32 *srcreg,*shiftreg;
878 srcreg = DECODE_RM_LONG_REGISTER(rl);
880 shiftreg = DECODE_RM_LONG_REGISTER(rh);
882 bit = *shiftreg & 0x1F;
884 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
887 u16 *srcreg,*shiftreg;
890 srcreg = DECODE_RM_WORD_REGISTER(rl);
892 shiftreg = DECODE_RM_WORD_REGISTER(rh);
894 bit = *shiftreg & 0xF;
895 mask = (u16)(0x1 << bit);
896 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
900 DECODE_CLEAR_SEGOVR();
904 /****************************************************************************
906 Handles opcode 0x0f,0xb4
907 ****************************************************************************/
908 void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2))
915 DECODE_PRINTF("LFS\t");
916 FETCH_DECODE_MODRM(mod, rh, rl);
918 dstreg = DECODE_RM_WORD_REGISTER(rh);
920 srcoffset = decode_rmXX_address(mod, rl);
923 *dstreg = fetch_data_word(srcoffset);
924 M.x86.R_FS = fetch_data_word(srcoffset + 2);
925 } else { /* register to register */
929 DECODE_CLEAR_SEGOVR();
933 /****************************************************************************
935 Handles opcode 0x0f,0xb5
936 ****************************************************************************/
937 void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2))
944 DECODE_PRINTF("LGS\t");
945 FETCH_DECODE_MODRM(mod, rh, rl);
947 dstreg = DECODE_RM_WORD_REGISTER(rh);
949 srcoffset = decode_rmXX_address(mod, rl);
952 *dstreg = fetch_data_word(srcoffset);
953 M.x86.R_GS = fetch_data_word(srcoffset + 2);
954 } else { /* register to register */
958 DECODE_CLEAR_SEGOVR();
962 /****************************************************************************
964 Handles opcode 0x0f,0xb6
965 ****************************************************************************/
966 void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2))
972 DECODE_PRINTF("MOVZX\t");
973 FETCH_DECODE_MODRM(mod, rh, rl);
975 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
979 destreg = DECODE_RM_LONG_REGISTER(rh);
981 srcoffset = decode_rmXX_address(mod, rl);
982 srcval = fetch_data_byte(srcoffset);
990 destreg = DECODE_RM_WORD_REGISTER(rh);
992 srcoffset = decode_rmXX_address(mod, rl);
993 srcval = fetch_data_byte(srcoffset);
998 } else { /* register to register */
999 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1003 destreg = DECODE_RM_LONG_REGISTER(rh);
1005 srcreg = DECODE_RM_BYTE_REGISTER(rl);
1006 DECODE_PRINTF("\n");
1013 destreg = DECODE_RM_WORD_REGISTER(rh);
1015 srcreg = DECODE_RM_BYTE_REGISTER(rl);
1016 DECODE_PRINTF("\n");
1021 DECODE_CLEAR_SEGOVR();
1025 /****************************************************************************
1027 Handles opcode 0x0f,0xb7
1028 ****************************************************************************/
1029 void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2))
1038 DECODE_PRINTF("MOVZX\t");
1039 FETCH_DECODE_MODRM(mod, rh, rl);
1041 destreg = DECODE_RM_LONG_REGISTER(rh);
1043 srcoffset = decode_rmXX_address(mod, rl);
1044 srcval = fetch_data_word(srcoffset);
1045 DECODE_PRINTF("\n");
1048 } else { /* register to register */
1049 destreg = DECODE_RM_LONG_REGISTER(rh);
1051 srcreg = DECODE_RM_WORD_REGISTER(rl);
1052 DECODE_PRINTF("\n");
1056 DECODE_CLEAR_SEGOVR();
1060 /****************************************************************************
1062 Handles opcode 0x0f,0xba
1063 ****************************************************************************/
1064 void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2))
1072 FETCH_DECODE_MODRM(mod, rh, rl);
1075 DECODE_PRINTF("BT\t");
1078 DECODE_PRINTF("BTS\t");
1081 DECODE_PRINTF("BTR\t");
1084 DECODE_PRINTF("BTC\t");
1087 DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
1089 printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
1090 M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
1095 srcoffset = decode_rmXX_address(mod, rl);
1096 shift = fetch_byte_imm();
1097 DECODE_PRINTF2(",%d\n", shift);
1100 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1104 srcval = fetch_data_long(srcoffset);
1105 mask = (0x1 << bit);
1106 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
1109 store_data_long(srcoffset, srcval | mask);
1112 store_data_long(srcoffset, srcval & ~mask);
1115 store_data_long(srcoffset, srcval ^ mask);
1124 srcval = fetch_data_word(srcoffset);
1125 mask = (0x1 << bit);
1126 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
1129 store_data_word(srcoffset, srcval | mask);
1132 store_data_word(srcoffset, srcval & ~mask);
1135 store_data_word(srcoffset, srcval ^ mask);
1141 } else { /* register to register */
1142 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1146 srcreg = DECODE_RM_LONG_REGISTER(rl);
1147 shift = fetch_byte_imm();
1148 DECODE_PRINTF2(",%d\n", shift);
1151 mask = (0x1 << bit);
1152 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
1170 srcreg = DECODE_RM_WORD_REGISTER(rl);
1171 shift = fetch_byte_imm();
1172 DECODE_PRINTF2(",%d\n", shift);
1175 mask = (0x1 << bit);
1176 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
1192 DECODE_CLEAR_SEGOVR();
1196 /****************************************************************************
1198 Handles opcode 0x0f,0xbb
1199 ****************************************************************************/
1200 void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2))
1207 DECODE_PRINTF("BTC\t");
1208 FETCH_DECODE_MODRM(mod, rh, rl);
1210 srcoffset = decode_rmXX_address(mod, rl);
1212 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1216 shiftreg = DECODE_RM_LONG_REGISTER(rh);
1218 bit = *shiftreg & 0x1F;
1219 disp = (s16)*shiftreg >> 5;
1220 srcval = fetch_data_long(srcoffset+disp);
1221 mask = (0x1 << bit);
1222 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
1223 store_data_long(srcoffset+disp, srcval ^ mask);
1228 shiftreg = DECODE_RM_WORD_REGISTER(rh);
1230 bit = *shiftreg & 0xF;
1231 disp = (s16)*shiftreg >> 4;
1232 srcval = fetch_data_word(srcoffset+disp);
1233 mask = (u16)(0x1 << bit);
1234 CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
1235 store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
1237 } else { /* register to register */
1238 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1239 u32 *srcreg,*shiftreg;
1242 srcreg = DECODE_RM_LONG_REGISTER(rl);
1244 shiftreg = DECODE_RM_LONG_REGISTER(rh);
1246 bit = *shiftreg & 0x1F;
1247 mask = (0x1 << bit);
1248 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
1251 u16 *srcreg,*shiftreg;
1254 srcreg = DECODE_RM_WORD_REGISTER(rl);
1256 shiftreg = DECODE_RM_WORD_REGISTER(rh);
1258 bit = *shiftreg & 0xF;
1259 mask = (u16)(0x1 << bit);
1260 CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
1264 DECODE_CLEAR_SEGOVR();
1268 /****************************************************************************
1270 Handles opcode 0x0f,0xbc
1271 ****************************************************************************/
1272 void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
1278 DECODE_PRINTF("BSF\n");
1279 FETCH_DECODE_MODRM(mod, rh, rl);
1281 srcoffset = decode_rmXX_address(mod, rl);
1283 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1284 u32 srcval, *dstreg;
1286 dstreg = DECODE_RM_LONG_REGISTER(rh);
1288 srcval = fetch_data_long(srcoffset);
1289 CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
1290 for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
1291 if ((srcval >> *dstreg) & 1) break;
1293 u16 srcval, *dstreg;
1295 dstreg = DECODE_RM_WORD_REGISTER(rh);
1297 srcval = fetch_data_word(srcoffset);
1298 CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
1299 for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
1300 if ((srcval >> *dstreg) & 1) break;
1302 } else { /* register to register */
1303 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1304 u32 *srcreg, *dstreg;
1306 srcreg = DECODE_RM_LONG_REGISTER(rl);
1308 dstreg = DECODE_RM_LONG_REGISTER(rh);
1310 CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
1311 for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
1312 if ((*srcreg >> *dstreg) & 1) break;
1314 u16 *srcreg, *dstreg;
1316 srcreg = DECODE_RM_WORD_REGISTER(rl);
1318 dstreg = DECODE_RM_WORD_REGISTER(rh);
1320 CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
1321 for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
1322 if ((*srcreg >> *dstreg) & 1) break;
1325 DECODE_CLEAR_SEGOVR();
1329 /****************************************************************************
1331 Handles opcode 0x0f,0xbd
1332 ****************************************************************************/
1333 void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
1339 DECODE_PRINTF("BSF\n");
1340 FETCH_DECODE_MODRM(mod, rh, rl);
1342 srcoffset = decode_rmXX_address(mod, rl);
1344 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1345 u32 srcval, *dstreg;
1347 dstreg = DECODE_RM_LONG_REGISTER(rh);
1349 srcval = fetch_data_long(srcoffset);
1350 CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
1351 for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
1352 if ((srcval >> *dstreg) & 1) break;
1354 u16 srcval, *dstreg;
1356 dstreg = DECODE_RM_WORD_REGISTER(rh);
1358 srcval = fetch_data_word(srcoffset);
1359 CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
1360 for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
1361 if ((srcval >> *dstreg) & 1) break;
1363 } else { /* register to register */
1364 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1365 u32 *srcreg, *dstreg;
1367 srcreg = DECODE_RM_LONG_REGISTER(rl);
1369 dstreg = DECODE_RM_LONG_REGISTER(rh);
1371 CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
1372 for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
1373 if ((*srcreg >> *dstreg) & 1) break;
1375 u16 *srcreg, *dstreg;
1377 srcreg = DECODE_RM_WORD_REGISTER(rl);
1379 dstreg = DECODE_RM_WORD_REGISTER(rh);
1381 CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
1382 for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
1383 if ((*srcreg >> *dstreg) & 1) break;
1386 DECODE_CLEAR_SEGOVR();
1390 /****************************************************************************
1392 Handles opcode 0x0f,0xbe
1393 ****************************************************************************/
1394 void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2))
1400 DECODE_PRINTF("MOVSX\t");
1401 FETCH_DECODE_MODRM(mod, rh, rl);
1403 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1407 destreg = DECODE_RM_LONG_REGISTER(rh);
1409 srcoffset = decode_rmXX_address(mod, rl);
1410 srcval = (s32)((s8)fetch_data_byte(srcoffset));
1411 DECODE_PRINTF("\n");
1418 destreg = DECODE_RM_WORD_REGISTER(rh);
1420 srcoffset = decode_rmXX_address(mod, rl);
1421 srcval = (s16)((s8)fetch_data_byte(srcoffset));
1422 DECODE_PRINTF("\n");
1426 } else { /* register to register */
1427 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
1431 destreg = DECODE_RM_LONG_REGISTER(rh);
1433 srcreg = DECODE_RM_BYTE_REGISTER(rl);
1434 DECODE_PRINTF("\n");
1436 *destreg = (s32)((s8)*srcreg);
1441 destreg = DECODE_RM_WORD_REGISTER(rh);
1443 srcreg = DECODE_RM_BYTE_REGISTER(rl);
1444 DECODE_PRINTF("\n");
1446 *destreg = (s16)((s8)*srcreg);
1449 DECODE_CLEAR_SEGOVR();
1453 /****************************************************************************
1455 Handles opcode 0x0f,0xbf
1456 ****************************************************************************/
1457 void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2))
1466 DECODE_PRINTF("MOVSX\t");
1467 FETCH_DECODE_MODRM(mod, rh, rl);
1469 destreg = DECODE_RM_LONG_REGISTER(rh);
1471 srcoffset = decode_rmXX_address(mod, rl);
1472 srcval = (s32)((s16)fetch_data_word(srcoffset));
1473 DECODE_PRINTF("\n");
1476 } else { /* register to register */
1477 destreg = DECODE_RM_LONG_REGISTER(rh);
1479 srcreg = DECODE_RM_WORD_REGISTER(rl);
1480 DECODE_PRINTF("\n");
1482 *destreg = (s32)((s16)*srcreg);
1484 DECODE_CLEAR_SEGOVR();
1488 /***************************************************************************
1489 * Double byte operation code table:
1490 **************************************************************************/
1491 void (*x86emu_optab2[256])(u8) =
1493 /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */
1494 /* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */
1495 /* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */
1496 /* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */
1497 /* 0x04 */ x86emuOp2_illegal_op,
1498 /* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */
1499 /* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */
1500 /* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */
1501 /* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */
1502 /* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */
1503 /* 0x0a */ x86emuOp2_illegal_op,
1504 /* 0x0b */ x86emuOp2_illegal_op,
1505 /* 0x0c */ x86emuOp2_illegal_op,
1506 /* 0x0d */ x86emuOp2_illegal_op,
1507 /* 0x0e */ x86emuOp2_illegal_op,
1508 /* 0x0f */ x86emuOp2_illegal_op,
1510 /* 0x10 */ x86emuOp2_illegal_op,
1511 /* 0x11 */ x86emuOp2_illegal_op,
1512 /* 0x12 */ x86emuOp2_illegal_op,
1513 /* 0x13 */ x86emuOp2_illegal_op,
1514 /* 0x14 */ x86emuOp2_illegal_op,
1515 /* 0x15 */ x86emuOp2_illegal_op,
1516 /* 0x16 */ x86emuOp2_illegal_op,
1517 /* 0x17 */ x86emuOp2_illegal_op,
1518 /* 0x18 */ x86emuOp2_illegal_op,
1519 /* 0x19 */ x86emuOp2_illegal_op,
1520 /* 0x1a */ x86emuOp2_illegal_op,
1521 /* 0x1b */ x86emuOp2_illegal_op,
1522 /* 0x1c */ x86emuOp2_illegal_op,
1523 /* 0x1d */ x86emuOp2_illegal_op,
1524 /* 0x1e */ x86emuOp2_illegal_op,
1525 /* 0x1f */ x86emuOp2_illegal_op,
1527 /* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */
1528 /* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */
1529 /* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */
1530 /* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */
1531 /* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */
1532 /* 0x25 */ x86emuOp2_illegal_op,
1533 /* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */
1534 /* 0x27 */ x86emuOp2_illegal_op,
1535 /* 0x28 */ x86emuOp2_illegal_op,
1536 /* 0x29 */ x86emuOp2_illegal_op,
1537 /* 0x2a */ x86emuOp2_illegal_op,
1538 /* 0x2b */ x86emuOp2_illegal_op,
1539 /* 0x2c */ x86emuOp2_illegal_op,
1540 /* 0x2d */ x86emuOp2_illegal_op,
1541 /* 0x2e */ x86emuOp2_illegal_op,
1542 /* 0x2f */ x86emuOp2_illegal_op,
1544 /* 0x30 */ x86emuOp2_illegal_op,
1545 /* 0x31 */ x86emuOp2_illegal_op,
1546 /* 0x32 */ x86emuOp2_illegal_op,
1547 /* 0x33 */ x86emuOp2_illegal_op,
1548 /* 0x34 */ x86emuOp2_illegal_op,
1549 /* 0x35 */ x86emuOp2_illegal_op,
1550 /* 0x36 */ x86emuOp2_illegal_op,
1551 /* 0x37 */ x86emuOp2_illegal_op,
1552 /* 0x38 */ x86emuOp2_illegal_op,
1553 /* 0x39 */ x86emuOp2_illegal_op,
1554 /* 0x3a */ x86emuOp2_illegal_op,
1555 /* 0x3b */ x86emuOp2_illegal_op,
1556 /* 0x3c */ x86emuOp2_illegal_op,
1557 /* 0x3d */ x86emuOp2_illegal_op,
1558 /* 0x3e */ x86emuOp2_illegal_op,
1559 /* 0x3f */ x86emuOp2_illegal_op,
1561 /* 0x40 */ x86emuOp2_illegal_op,
1562 /* 0x41 */ x86emuOp2_illegal_op,
1563 /* 0x42 */ x86emuOp2_illegal_op,
1564 /* 0x43 */ x86emuOp2_illegal_op,
1565 /* 0x44 */ x86emuOp2_illegal_op,
1566 /* 0x45 */ x86emuOp2_illegal_op,
1567 /* 0x46 */ x86emuOp2_illegal_op,
1568 /* 0x47 */ x86emuOp2_illegal_op,
1569 /* 0x48 */ x86emuOp2_illegal_op,
1570 /* 0x49 */ x86emuOp2_illegal_op,
1571 /* 0x4a */ x86emuOp2_illegal_op,
1572 /* 0x4b */ x86emuOp2_illegal_op,
1573 /* 0x4c */ x86emuOp2_illegal_op,
1574 /* 0x4d */ x86emuOp2_illegal_op,
1575 /* 0x4e */ x86emuOp2_illegal_op,
1576 /* 0x4f */ x86emuOp2_illegal_op,
1578 /* 0x50 */ x86emuOp2_illegal_op,
1579 /* 0x51 */ x86emuOp2_illegal_op,
1580 /* 0x52 */ x86emuOp2_illegal_op,
1581 /* 0x53 */ x86emuOp2_illegal_op,
1582 /* 0x54 */ x86emuOp2_illegal_op,
1583 /* 0x55 */ x86emuOp2_illegal_op,
1584 /* 0x56 */ x86emuOp2_illegal_op,
1585 /* 0x57 */ x86emuOp2_illegal_op,
1586 /* 0x58 */ x86emuOp2_illegal_op,
1587 /* 0x59 */ x86emuOp2_illegal_op,
1588 /* 0x5a */ x86emuOp2_illegal_op,
1589 /* 0x5b */ x86emuOp2_illegal_op,
1590 /* 0x5c */ x86emuOp2_illegal_op,
1591 /* 0x5d */ x86emuOp2_illegal_op,
1592 /* 0x5e */ x86emuOp2_illegal_op,
1593 /* 0x5f */ x86emuOp2_illegal_op,
1595 /* 0x60 */ x86emuOp2_illegal_op,
1596 /* 0x61 */ x86emuOp2_illegal_op,
1597 /* 0x62 */ x86emuOp2_illegal_op,
1598 /* 0x63 */ x86emuOp2_illegal_op,
1599 /* 0x64 */ x86emuOp2_illegal_op,
1600 /* 0x65 */ x86emuOp2_illegal_op,
1601 /* 0x66 */ x86emuOp2_illegal_op,
1602 /* 0x67 */ x86emuOp2_illegal_op,
1603 /* 0x68 */ x86emuOp2_illegal_op,
1604 /* 0x69 */ x86emuOp2_illegal_op,
1605 /* 0x6a */ x86emuOp2_illegal_op,
1606 /* 0x6b */ x86emuOp2_illegal_op,
1607 /* 0x6c */ x86emuOp2_illegal_op,
1608 /* 0x6d */ x86emuOp2_illegal_op,
1609 /* 0x6e */ x86emuOp2_illegal_op,
1610 /* 0x6f */ x86emuOp2_illegal_op,
1612 /* 0x70 */ x86emuOp2_illegal_op,
1613 /* 0x71 */ x86emuOp2_illegal_op,
1614 /* 0x72 */ x86emuOp2_illegal_op,
1615 /* 0x73 */ x86emuOp2_illegal_op,
1616 /* 0x74 */ x86emuOp2_illegal_op,
1617 /* 0x75 */ x86emuOp2_illegal_op,
1618 /* 0x76 */ x86emuOp2_illegal_op,
1619 /* 0x77 */ x86emuOp2_illegal_op,
1620 /* 0x78 */ x86emuOp2_illegal_op,
1621 /* 0x79 */ x86emuOp2_illegal_op,
1622 /* 0x7a */ x86emuOp2_illegal_op,
1623 /* 0x7b */ x86emuOp2_illegal_op,
1624 /* 0x7c */ x86emuOp2_illegal_op,
1625 /* 0x7d */ x86emuOp2_illegal_op,
1626 /* 0x7e */ x86emuOp2_illegal_op,
1627 /* 0x7f */ x86emuOp2_illegal_op,
1629 /* 0x80 */ x86emuOp2_long_jump,
1630 /* 0x81 */ x86emuOp2_long_jump,
1631 /* 0x82 */ x86emuOp2_long_jump,
1632 /* 0x83 */ x86emuOp2_long_jump,
1633 /* 0x84 */ x86emuOp2_long_jump,
1634 /* 0x85 */ x86emuOp2_long_jump,
1635 /* 0x86 */ x86emuOp2_long_jump,
1636 /* 0x87 */ x86emuOp2_long_jump,
1637 /* 0x88 */ x86emuOp2_long_jump,
1638 /* 0x89 */ x86emuOp2_long_jump,
1639 /* 0x8a */ x86emuOp2_long_jump,
1640 /* 0x8b */ x86emuOp2_long_jump,
1641 /* 0x8c */ x86emuOp2_long_jump,
1642 /* 0x8d */ x86emuOp2_long_jump,
1643 /* 0x8e */ x86emuOp2_long_jump,
1644 /* 0x8f */ x86emuOp2_long_jump,
1646 /* 0x90 */ x86emuOp2_set_byte,
1647 /* 0x91 */ x86emuOp2_set_byte,
1648 /* 0x92 */ x86emuOp2_set_byte,
1649 /* 0x93 */ x86emuOp2_set_byte,
1650 /* 0x94 */ x86emuOp2_set_byte,
1651 /* 0x95 */ x86emuOp2_set_byte,
1652 /* 0x96 */ x86emuOp2_set_byte,
1653 /* 0x97 */ x86emuOp2_set_byte,
1654 /* 0x98 */ x86emuOp2_set_byte,
1655 /* 0x99 */ x86emuOp2_set_byte,
1656 /* 0x9a */ x86emuOp2_set_byte,
1657 /* 0x9b */ x86emuOp2_set_byte,
1658 /* 0x9c */ x86emuOp2_set_byte,
1659 /* 0x9d */ x86emuOp2_set_byte,
1660 /* 0x9e */ x86emuOp2_set_byte,
1661 /* 0x9f */ x86emuOp2_set_byte,
1663 /* 0xa0 */ x86emuOp2_push_FS,
1664 /* 0xa1 */ x86emuOp2_pop_FS,
1665 /* 0xa2 */ x86emuOp2_illegal_op,
1666 /* 0xa3 */ x86emuOp2_bt_R,
1667 /* 0xa4 */ x86emuOp2_shld_IMM,
1668 /* 0xa5 */ x86emuOp2_shld_CL,
1669 /* 0xa6 */ x86emuOp2_illegal_op,
1670 /* 0xa7 */ x86emuOp2_illegal_op,
1671 /* 0xa8 */ x86emuOp2_push_GS,
1672 /* 0xa9 */ x86emuOp2_pop_GS,
1673 /* 0xaa */ x86emuOp2_illegal_op,
1674 /* 0xab */ x86emuOp2_bt_R,
1675 /* 0xac */ x86emuOp2_shrd_IMM,
1676 /* 0xad */ x86emuOp2_shrd_CL,
1677 /* 0xae */ x86emuOp2_illegal_op,
1678 /* 0xaf */ x86emuOp2_imul_R_RM,
1680 /* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */
1681 /* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */
1682 /* 0xb2 */ x86emuOp2_lss_R_IMM,
1683 /* 0xb3 */ x86emuOp2_btr_R,
1684 /* 0xb4 */ x86emuOp2_lfs_R_IMM,
1685 /* 0xb5 */ x86emuOp2_lgs_R_IMM,
1686 /* 0xb6 */ x86emuOp2_movzx_byte_R_RM,
1687 /* 0xb7 */ x86emuOp2_movzx_word_R_RM,
1688 /* 0xb8 */ x86emuOp2_illegal_op,
1689 /* 0xb9 */ x86emuOp2_illegal_op,
1690 /* 0xba */ x86emuOp2_btX_I,
1691 /* 0xbb */ x86emuOp2_btc_R,
1692 /* 0xbc */ x86emuOp2_bsf,
1693 /* 0xbd */ x86emuOp2_bsr,
1694 /* 0xbe */ x86emuOp2_movsx_byte_R_RM,
1695 /* 0xbf */ x86emuOp2_movsx_word_R_RM,
1697 /* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */
1698 /* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */
1699 /* 0xc2 */ x86emuOp2_illegal_op,
1700 /* 0xc3 */ x86emuOp2_illegal_op,
1701 /* 0xc4 */ x86emuOp2_illegal_op,
1702 /* 0xc5 */ x86emuOp2_illegal_op,
1703 /* 0xc6 */ x86emuOp2_illegal_op,
1704 /* 0xc7 */ x86emuOp2_illegal_op,
1705 /* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */
1706 /* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */
1707 /* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */
1708 /* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */
1709 /* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */
1710 /* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */
1711 /* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */
1712 /* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */
1714 /* 0xd0 */ x86emuOp2_illegal_op,
1715 /* 0xd1 */ x86emuOp2_illegal_op,
1716 /* 0xd2 */ x86emuOp2_illegal_op,
1717 /* 0xd3 */ x86emuOp2_illegal_op,
1718 /* 0xd4 */ x86emuOp2_illegal_op,
1719 /* 0xd5 */ x86emuOp2_illegal_op,
1720 /* 0xd6 */ x86emuOp2_illegal_op,
1721 /* 0xd7 */ x86emuOp2_illegal_op,
1722 /* 0xd8 */ x86emuOp2_illegal_op,
1723 /* 0xd9 */ x86emuOp2_illegal_op,
1724 /* 0xda */ x86emuOp2_illegal_op,
1725 /* 0xdb */ x86emuOp2_illegal_op,
1726 /* 0xdc */ x86emuOp2_illegal_op,
1727 /* 0xdd */ x86emuOp2_illegal_op,
1728 /* 0xde */ x86emuOp2_illegal_op,
1729 /* 0xdf */ x86emuOp2_illegal_op,
1731 /* 0xe0 */ x86emuOp2_illegal_op,
1732 /* 0xe1 */ x86emuOp2_illegal_op,
1733 /* 0xe2 */ x86emuOp2_illegal_op,
1734 /* 0xe3 */ x86emuOp2_illegal_op,
1735 /* 0xe4 */ x86emuOp2_illegal_op,
1736 /* 0xe5 */ x86emuOp2_illegal_op,
1737 /* 0xe6 */ x86emuOp2_illegal_op,
1738 /* 0xe7 */ x86emuOp2_illegal_op,
1739 /* 0xe8 */ x86emuOp2_illegal_op,
1740 /* 0xe9 */ x86emuOp2_illegal_op,
1741 /* 0xea */ x86emuOp2_illegal_op,
1742 /* 0xeb */ x86emuOp2_illegal_op,
1743 /* 0xec */ x86emuOp2_illegal_op,
1744 /* 0xed */ x86emuOp2_illegal_op,
1745 /* 0xee */ x86emuOp2_illegal_op,
1746 /* 0xef */ x86emuOp2_illegal_op,
1748 /* 0xf0 */ x86emuOp2_illegal_op,
1749 /* 0xf1 */ x86emuOp2_illegal_op,
1750 /* 0xf2 */ x86emuOp2_illegal_op,
1751 /* 0xf3 */ x86emuOp2_illegal_op,
1752 /* 0xf4 */ x86emuOp2_illegal_op,
1753 /* 0xf5 */ x86emuOp2_illegal_op,
1754 /* 0xf6 */ x86emuOp2_illegal_op,
1755 /* 0xf7 */ x86emuOp2_illegal_op,
1756 /* 0xf8 */ x86emuOp2_illegal_op,
1757 /* 0xf9 */ x86emuOp2_illegal_op,
1758 /* 0xfa */ x86emuOp2_illegal_op,
1759 /* 0xfb */ x86emuOp2_illegal_op,
1760 /* 0xfc */ x86emuOp2_illegal_op,
1761 /* 0xfd */ x86emuOp2_illegal_op,
1762 /* 0xfe */ x86emuOp2_illegal_op,
1763 /* 0xff */ x86emuOp2_illegal_op,