1 /* (c) 2005 Linux Networx GPL see COPYING for details */
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/cardbus.h>
9 /* I don't think this code is quite correct but it is close.
10 * Anyone with a cardbus bridge and a little time should be able
11 * to make it usable quickly. -- Eric Biederman 24 March 2005
15 * IO should be max 256 bytes. However, since we may
16 * have a P2P bridge below a cardbus bridge, we need 4K.
18 #define CARDBUS_IO_SIZE (4096)
19 #define CARDBUS_MEM_SIZE (32*1024*1024)
21 static void cardbus_record_bridge_resource(
22 device_t dev, resource_t moving, resource_t min_size,
23 unsigned index, unsigned long type)
25 /* Initiliaze the constraints on the current bus */
26 struct resource *resource;
31 resource = new_resource(dev, index);
35 while((moving & step) == 0) {
39 resource->gran = gran;
40 resource->align = gran;
41 resource->limit = moving | (step - 1);
42 resource->flags = type;
43 /* Don't let the minimum size exceed what we
44 * can put in the resource.
46 if ((min_size - 1) > resource->limit) {
47 min_size = resource->limit + 1;
49 resource->size = min_size;
54 static void cardbus_size_bridge_resource(device_t dev, unsigned index)
56 struct resource *resource;
58 resource = find_resource(dev, index);
60 min_size = resource->size;
61 compute_allocate_resource(&dev->link[0], resource,
62 resource->flags, resource->flags);
63 /* Allways allocate at least the miniumum size to a
64 * cardbus bridge in case a new card is plugged in.
66 if (resource->size < min_size) {
67 resource->size = min_size;
72 void cardbus_read_resources(device_t dev)
74 resource_t moving_base, moving_limit, moving;
79 /* See if needs a card control registers base address */
81 pci_get_resource(dev, PCI_BASE_ADDRESS_0);
83 compact_resources(dev);
85 /* See which bridge I/O resources are implemented */
86 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0);
87 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0);
88 moving = moving_base & moving_limit;
90 /* Initialize the io space constraints on the current bus */
91 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
92 PCI_CB_IO_BASE_0, IORESOURCE_IO);
93 cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0);
95 /* See which bridge I/O resources are implemented */
96 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1);
97 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1);
98 moving = moving_base & moving_limit;
100 /* Initialize the io space constraints on the current bus */
101 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
102 PCI_CB_IO_BASE_1, IORESOURCE_IO);
104 /* If I can enable prefetch for mem0 */
105 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
106 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
107 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
108 ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
109 pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl);
110 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
112 /* See which bridge memory resources are implemented */
113 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0);
114 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0);
115 moving = moving_base & moving_limit;
117 /* Initialize the memory space constraints on the current bus */
118 type = IORESOURCE_MEM;
119 if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
120 type |= IORESOURCE_PREFETCH;
122 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
123 PCI_CB_MEMORY_BASE_0, type);
124 if (type & IORESOURCE_PREFETCH) {
125 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0);
128 /* See which bridge memory resources are implemented */
129 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1);
130 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1);
131 moving = moving_base & moving_limit;
133 /* Initialize the memory space constraints on the current bus */
134 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
135 PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM);
136 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1);
138 compact_resources(dev);
141 void cardbus_enable_resources(device_t dev)
144 ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
145 ctrl |= (dev->link[0].bridge_ctrl & (
146 PCI_BRIDGE_CTL_PARITY |
147 PCI_BRIDGE_CTL_SERR |
148 PCI_BRIDGE_CTL_NO_ISA |
150 PCI_BRIDGE_CTL_MASTER_ABORT |
151 PCI_BRIDGE_CTL_BUS_RESET));
152 ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); /* error check */
153 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
154 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
156 pci_dev_enable_resources(dev);
158 enable_childrens_resources(dev);
161 unsigned int cardbus_scan_bus(struct bus *bus,
162 unsigned min_devfn, unsigned max_devfn,
165 return pci_scan_bus(bus, min_devfn, max_devfn, max);
169 unsigned int cardbus_scan_bridge(device_t dev, unsigned int max)
175 printk_spew("%s for %s\n", __func__, dev_path(dev));
181 /* Set up the primary, secondary and subordinate bus numbers. We have
182 * no idea how many buses are behind this bridge yet, so we set the
183 * subordinate bus number to 0xff for the moment.
185 bus->secondary = ++max;
186 bus->subordinate = 0xff;
188 /* Clear all status bits and turn off memory, I/O and master enables. */
189 cr = pci_read_config16(dev, PCI_COMMAND);
190 pci_write_config16(dev, PCI_COMMAND, 0x0000);
191 pci_write_config16(dev, PCI_STATUS, 0xffff);
194 * Read the existing primary/secondary/subordinate bus
195 * number configuration.
197 buses = pci_read_config32(dev, PCI_CB_PRIMARY_BUS);
199 /* Configure the bus numbers for this bridge: the configuration
200 * transactions will not be propagated by the bridge if it is not
201 * correctly configured.
204 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
205 ((unsigned int) (bus->secondary) << 8) |
206 ((unsigned int) (bus->subordinate) << 16));
207 pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses);
209 /* Now we can scan all subordinate buses
210 * i.e. the bus behind the bridge.
212 max = cardbus_scan_bus(bus, 0x00, 0xff, max);
214 /* We know the number of buses behind this bridge. Set the subordinate
215 * bus number to its real value.
217 bus->subordinate = max;
218 buses = (buses & 0xff00ffff) |
219 ((unsigned int) (bus->subordinate) << 16);
220 pci_write_config32(dev, PCI_CB_PRIMARY_BUS, buses);
221 pci_write_config16(dev, PCI_COMMAND, cr);
223 printk_spew("%s returns max %d\n", __func__, max);
227 struct device_operations default_cardbus_ops_bus = {
228 .read_resources = cardbus_read_resources,
229 .set_resources = pci_dev_set_resources,
230 .enable_resources = cardbus_enable_resources,
232 .scan_bus = cardbus_scan_bridge,
234 .reset_bus = pci_bus_reset,