2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2005 Ronald G. Minnich <rminnich@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/cardbus.h>
28 /* I don't think this code is quite correct but it is close.
29 * Anyone with a cardbus bridge and a little time should be able
30 * to make it usable quickly. -- Eric Biederman 24 March 2005
34 * IO should be max 256 bytes. However, since we may
35 * have a P2P bridge below a cardbus bridge, we need 4K.
37 #define CARDBUS_IO_SIZE (4096)
38 #define CARDBUS_MEM_SIZE (32*1024*1024)
40 static void cardbus_record_bridge_resource(
41 device_t dev, resource_t moving, resource_t min_size,
42 unsigned index, unsigned long type)
44 /* Initialize the constraints on the current bus. */
45 struct resource *resource;
50 resource = new_resource(dev, index);
54 while ((moving & step) == 0) {
58 resource->gran = gran;
59 resource->align = gran;
60 resource->limit = moving | (step - 1);
61 resource->flags = type;
62 /* Don't let the minimum size exceed what we
63 * can put in the resource.
65 if ((min_size - 1) > resource->limit) {
66 min_size = resource->limit + 1;
68 resource->size = min_size;
73 static void cardbus_size_bridge_resource(device_t dev, unsigned index)
75 struct resource *resource;
77 resource = find_resource(dev, index);
79 min_size = resource->size;
80 /* Allways allocate at least the miniumum size to a
81 * cardbus bridge in case a new card is plugged in.
83 if (resource->size < min_size) {
84 resource->size = min_size;
89 void cardbus_read_resources(device_t dev)
91 resource_t moving_base, moving_limit, moving;
95 /* See if needs a card control registers base address */
97 pci_get_resource(dev, PCI_BASE_ADDRESS_0);
99 compact_resources(dev);
101 /* See which bridge I/O resources are implemented */
102 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0);
103 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0);
104 moving = moving_base & moving_limit;
106 /* Initialize the io space constraints on the current bus */
107 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
108 PCI_CB_IO_BASE_0, IORESOURCE_IO);
109 cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0);
111 /* See which bridge I/O resources are implemented */
112 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1);
113 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1);
114 moving = moving_base & moving_limit;
116 /* Initialize the io space constraints on the current bus */
117 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
118 PCI_CB_IO_BASE_1, IORESOURCE_IO);
120 /* If I can enable prefetch for mem0 */
121 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
122 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
123 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
124 ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
125 pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl);
126 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
128 /* See which bridge memory resources are implemented */
129 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0);
130 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0);
131 moving = moving_base & moving_limit;
133 /* Initialize the memory space constraints on the current bus */
134 type = IORESOURCE_MEM;
135 if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
136 type |= IORESOURCE_PREFETCH;
138 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
139 PCI_CB_MEMORY_BASE_0, type);
140 if (type & IORESOURCE_PREFETCH) {
141 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0);
144 /* See which bridge memory resources are implemented */
145 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1);
146 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1);
147 moving = moving_base & moving_limit;
149 /* Initialize the memory space constraints on the current bus */
150 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
151 PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM);
152 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1);
154 compact_resources(dev);
157 void cardbus_enable_resources(device_t dev)
160 ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
161 ctrl |= (dev->link[0].bridge_ctrl & (
162 PCI_BRIDGE_CTL_PARITY |
163 PCI_BRIDGE_CTL_SERR |
164 PCI_BRIDGE_CTL_NO_ISA |
166 PCI_BRIDGE_CTL_MASTER_ABORT |
167 PCI_BRIDGE_CTL_BUS_RESET));
168 ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR); /* error check */
169 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
170 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
172 pci_dev_enable_resources(dev);
174 enable_childrens_resources(dev);
177 struct device_operations default_cardbus_ops_bus = {
178 .read_resources = cardbus_read_resources,
179 .set_resources = pci_dev_set_resources,
180 .enable_resources = cardbus_enable_resources,
182 .scan_bus = pci_scan_bridge,
184 .reset_bus = pci_bus_reset,