1 // initialization function which are specific to i440fx chipset
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // Copyright (C) 2010 Isaku Yamahata <yamahata at valinux co jp>
7 // Split out from pciinit.c
9 // This file may be distributed under the terms of the GNU LGPLv3 license.
12 #include "config.h" // CONFIG_DEBUG_LEVEL
13 #include "util.h" // dprintf
14 #include "ioport.h" // outb
15 #include "pci.h" // pci_config_writeb
16 #include "pci_regs.h" // PCI_INTERRUPT_LINE
18 #include "dev-i440fx.h"
20 /* PIIX3/PIIX4 PCI to ISA bridge */
21 void piix_isa_bridge_init(u16 bdf, void *arg)
28 for (i = 0; i < 4; i++) {
30 /* set to trigger level */
31 elcr[irq >> 3] |= (1 << (irq & 7));
32 /* activate irq remapping in PIIX */
33 pci_config_writeb(bdf, 0x60 + i, irq);
37 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
41 void piix_ide_init(u16 bdf, void *arg)
43 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
44 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
45 pci_bios_allocate_regions(bdf, NULL);
48 /* PIIX4 Power Management device (for ACPI) */
49 void piix4_pm_init(u16 bdf, void *arg)
51 // acpi sci is hardwired to 9
52 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
54 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
55 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
56 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
57 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
60 #define PIIX4_ACPI_ENABLE 0xf1
61 #define PIIX4_ACPI_DISABLE 0xf0
62 #define PIIX4_GPE0_BLK 0xafe0
63 #define PIIX4_GPE0_BLK_LEN 4
65 void piix4_fadt_init(u16 bdf, void *arg)
67 struct fadt_descriptor_rev1 *fadt = arg;
68 fadt->acpi_enable = PIIX4_ACPI_ENABLE;
69 fadt->acpi_disable = PIIX4_ACPI_DISABLE;
70 fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
71 fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;