2 use ieee.std_logic_1164.all;
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4 architecture beh of sync is
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5 signal sync : std_logic_vector(1 to SYNC_STAGES);
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7 process(sys_clk, sys_res_n)
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9 if sys_res_n = '0' then
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10 sync <= (others => RESET_VALUE);
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11 elsif rising_edge(sys_clk) then
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13 for i in 2 to SYNC_STAGES loop
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14 sync(i) <= sync(i - 1);
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18 data_out <= sync(SYNC_STAGES);
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19 end architecture beh;
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