2 use ieee.std_logic_1164.all;
5 end entity debounce_tb;
7 architecture sim of debounce_tb is
8 component debounce_top is
11 sys_clk : in std_logic;
12 sys_res_n : in std_logic;
14 seg_a : out std_logic_vector(6 downto 0);
15 seg_b : out std_logic_vector(6 downto 0)
17 end component debounce_top;
19 signal sys_clk, sys_res_n : std_logic;
20 signal btn_a : std_logic;
21 signal seg_a, seg_b : std_logic_vector(6 downto 0);
22 signal stop : boolean := false;
28 sys_res_n => sys_res_n,