1 /* For starting coreboot in protected mode */
3 #include <arch/rom_segs.h>
8 /* This is the GDT for the ROM stage part of coreboot. It
9 * is different from the RAM stage GDT which is defined in
17 .word gdt_end - gdt -1 /* compute the table limit */
18 .long gdt /* we know the offset */
21 /* selgdt 0x08, flat code segment */
23 .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
25 /* selgdt 0x10,flat data segment */
27 .byte 0x00, 0x93, 0xcf, 0x00
33 * When we come here we are in protected mode. We expand
34 * the stack and copies the data segment from ROM to the
37 * After that, we call the chipset bootstrap routine that
38 * does what is left of the chipset initialization.
40 * NOTE aligned to 4 so that we are sure that the prefetch
41 * cache will be reloaded.
44 .globl protected_start
48 ljmp $ROM_CODE_SEG, $__protected_start
51 /* Save the BIST value */
54 post_code(0x10) /* post 10 */
56 movw $ROM_DATA_SEG, %ax
63 /* Restore the BIST value to %eax */