2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2005 Eswar Nallusamy, LANL
6 * Copyright (C) 2005 Tyan
7 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
8 * Copyright (C) 2007 coresystems GmbH
9 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
10 * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
11 * Copyright (C) 2008 VIA Technologies, Inc.
12 * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define CacheSize CONFIG_DCACHE_RAM_SIZE
29 #define CacheBase CONFIG_DCACHE_RAM_BASE
32 #include <cpu/x86/mtrr.h>
34 /* Save the BIST result */
45 /* Set the default memory type and enable fixed and variable MTRRs */
46 movl $MTRRdefType_MSR, %ecx
48 /* Enable Variable and Fixed MTRRs */
49 movl $0x00000c00, %eax
54 movl $fixed_mtrr_msr, %esi
59 jz clear_fixed_var_mtrr_out
65 jmp clear_fixed_var_mtrr
66 clear_fixed_var_mtrr_out:
70 movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
75 /* This assumes we never access addresses above 2^36 in CAR. */
77 movl $(~(CacheSize-1)|0x800),%eax
80 /* enable write base caching so we can do execute in place
86 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
87 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
89 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
91 movl $REAL_XIP_ROM_BASE, %eax
92 orl $MTRR_TYPE_WRBACK, %eax
97 movl $0x0000000f, %edx
98 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
101 movl $MTRRdefType_MSR, %ecx
103 /* Enable Variable and Fixed MTRRs */
104 movl $0x00000800, %eax
108 andl $0x9fffffff, %eax
111 /* Read the range with lodsl*/
113 movl $CacheBase, %esi
115 movl $(CacheSize>>2), %ecx
118 movl $CacheBase, %esi
120 movl $(CacheSize >> 2), %ecx
122 /* 0x5c5c5c5c is a memory test pattern.
123 * TODO: Check if everything works with the zero pattern as well. */
125 xorl $0x5c5c5c5c,%eax
128 movl CONFIG_XIP_ROM_BASE, %esi
130 movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
133 /* The key point of this CAR code is C7 cache does not turn into
134 * "no fill" mode, which is not compatible with general CAR code.
137 movl $(CacheBase + CacheSize - 4), %eax
141 testok: movb $0x40,%al
160 /* Restore the BIST result */
163 /* We need to set ebp ? No need */
165 pushl %eax /* bist */
167 /* We will not go back */
170 .long 0x250, 0x258, 0x259
171 .long 0x268, 0x269, 0x26A
172 .long 0x26B, 0x26C, 0x26D
175 .long 0x200, 0x201, 0x202, 0x203
176 .long 0x204, 0x205, 0x206, 0x207
177 .long 0x208, 0x209, 0x20A, 0x20B
178 .long 0x20C, 0x20D, 0x20E, 0x20F
179 .long 0x000 /* NULL, end of table */