2 * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
26 #include <console/console.h>
28 #include <cpu/p6/msr.h>
29 #include <cpu/p6/mtrr.h>
30 #include <cpu/k7/mtrr.h>
32 #define arraysize(x) (sizeof(x)/sizeof((x)[0]))
34 static unsigned int mtrr_msr[] = {
35 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
36 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
37 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
41 static void intel_enable_fixed_mtrr(void)
45 msr = rdmsr(MTRRdefType_MSR);
47 wrmsr(MTRRdefType_MSR, msr);
50 static void intel_enable_var_mtrr(void)
54 msr = rdmsr(MTRRdefType_MSR);
56 wrmsr(MTRRdefType_MSR, msr);
59 static inline void disable_cache(void)
63 /* Write back the cache and flush TLB */
66 "orl $0x40000000, %0\n\t"
74 static inline void enable_cache(void)
77 // turn cache back on.
80 "andl $0x9fffffff, %0\n\t"
86 /* setting variable mtrr, comes from linux kernel source */
87 static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
91 base.hi = basek >> 22;
92 base.lo = basek << 10;
94 if (sizek < 4*1024*1024) {
96 mask.lo = ~((sizek << 10) -1);
99 mask.hi = 0x0F & (~((sizek >> 22) -1));
106 // it is recommended that we disable and enable cache when we
111 zero.lo = zero.hi = 0;
112 /* The invalid bit is kept in the mask, so we simply clear the
113 relevant mask register to disable a range. */
114 wrmsr (MTRRphysMask_MSR(reg), zero);
116 /* Bit 32-35 of MTRRphysMask should be set to 1 */
119 wrmsr (MTRRphysBase_MSR(reg), base);
120 wrmsr (MTRRphysMask_MSR(reg), mask);
125 /* setting variable mtrr, comes from linux kernel source */
126 void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
131 // it is recommended that we disable and enable cache when we
135 /* The invalid bit is kept in the mask, so we simply clear the
136 relevant mask register to disable a range. */
138 zero.lo = zero.hi = 0;
139 wrmsr (MTRRphysMask_MSR(reg), zero);
141 /* Bit 32-35 of MTRRphysMask should be set to 1 */
143 basem.lo = base | type;
145 maskm.lo = ~(size - 1) | 0x800;
147 wrmsr (MTRRphysBase_MSR(reg), basem);
148 wrmsr (MTRRphysMask_MSR(reg), maskm);
151 // turn cache back on.
155 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
156 static inline unsigned int fms(unsigned int x)
160 __asm__("bsrl %1,%0\n\t"
163 "1:" : "=r" (r) : "g" (x));
167 /* fms: find least sigificant bit set */
168 static inline unsigned int fls(unsigned int x)
172 __asm__("bsfl %1,%0\n\t"
175 "1:" : "=r" (r) : "g" (x));
179 /* setting up variable and fixed mtrr
181 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
182 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
183 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
184 * requirement. So a 8K range must be 8K aligned not 4K aligned.
186 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
187 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
188 * A 124MB (128MB - 4MB SMA) example:
189 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
190 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
192 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
193 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
194 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
195 * The same 124MB example:
196 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
197 * or a 156MB (128MB + 32MB - 4MB SMA) example:
198 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
200 /* 2 MTRRS are reserved for the operating system */
203 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
206 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
209 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
211 msr.lo = msr.hi = 0; /* Shut up gcc */
212 for(i = first; i < last; i++) {
213 /* When I switch to a new msr read it in */
214 if (fixed_msr != i >> 3) {
215 /* But first write out the old msr */
216 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
218 wrmsr(mtrr_msr[fixed_msr], msr);
222 msr = rdmsr(mtrr_msr[fixed_msr]);
225 msr.lo &= ~(0xff << ((i&3)*8));
226 msr.lo |= type << ((i&3)*8);
228 msr.hi &= ~(0xff << ((i&3)*8));
229 msr.hi |= type << ((i&3)*8);
232 /* Write out the final msr */
233 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
235 wrmsr(mtrr_msr[fixed_msr], msr);
240 static unsigned fixed_mtrr_index(unsigned long addrk)
243 index = (addrk - 0) >> 6;
245 index = ((addrk - 8*64) >> 4) + 8;
248 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
250 if (index > NUM_FIXED_RANGES) {
251 index = NUM_FIXED_RANGES;
256 static unsigned int range_to_mtrr(unsigned int reg,
257 unsigned long range_startk, unsigned long range_sizek,
258 unsigned long next_range_startk)
260 if (!range_sizek || (reg >= BIOS_MTRRS)) {
264 unsigned long max_align, align;
266 /* Compute the maximum size I can make a range */
267 max_align = fls(range_startk);
268 align = fms(range_sizek);
269 if (align > max_align) {
273 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
274 reg, range_startk >>10, sizek >> 10);
275 intel_set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
276 range_startk += sizek;
277 range_sizek -= sizek;
278 if (reg >= BIOS_MTRRS)
284 void setup_mtrrs(struct mem_range *mem)
286 /* Try this the simple way of incrementally adding together
287 * mtrrs. If this doesn't work out we can get smart again
288 * and clear out the mtrrs.
290 struct mem_range *memp;
291 unsigned long range_startk, range_sizek;
295 /* Initialized the fixed_mtrrs to uncached */
296 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
297 0, NUM_FIXED_RANGES);
298 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHABLE);
300 /* Now see which of the fixed mtrrs cover ram.
302 for(memp = mem; memp->sizek; memp++) {
303 unsigned int start_mtrr;
304 unsigned int last_mtrr;
305 start_mtrr = fixed_mtrr_index(memp->basek);
306 last_mtrr = fixed_mtrr_index(memp->basek + memp->sizek);
307 if (start_mtrr >= NUM_FIXED_RANGES) {
310 printk_debug("Setting fixed MTRRs(%d-%d) type: WB\n",
311 start_mtrr, last_mtrr);
312 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
314 printk_debug("DONE fixed MTRRs\n");
315 /* Cache as many memory areas as possible */
316 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
317 * In some cases it is definitely possible to do better.
322 for (memp = mem; memp->sizek; memp++) {
323 /* See if I can merge with the last range
324 * Either I am below 1M and the fixed mtrrs handle it, or
327 if ((memp->basek <= 1024) || (range_startk + range_sizek == memp->basek)) {
328 unsigned long endk = memp->basek + memp->sizek;
329 range_sizek = endk - range_startk;
332 /* Write the range mtrrs */
333 if (range_sizek != 0) {
334 reg = range_to_mtrr(reg, range_startk, range_sizek, memp->basek);
337 if (reg >= BIOS_MTRRS)
340 /* Allocate an msr */
341 range_startk = memp->basek;
342 range_sizek = memp->sizek;
344 /* Write the last range */
345 reg = range_to_mtrr(reg, range_startk, range_sizek, 0);
346 printk_debug("DONE variable MTRRs\n");
347 printk_debug("Clear out the extra MTRR's\n");
348 /* Clear out the extra MTRR's */
350 intel_set_var_mtrr(reg++, 0, 0, 0);
352 /* enable fixed MTRR */
353 printk_debug("call intel_enable_fixed_mtrr()\n");
354 intel_enable_fixed_mtrr();
355 printk_debug("call intel_enable_var_mtrr()\n");
356 intel_enable_var_mtrr();
357 printk_debug("Leave %s\n", __FUNCTION__);