2 * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
29 static char rcsid[] = "$Id$";
32 #include <console/console.h>
34 #include <cpu/p6/msr.h>
35 #include <cpu/p6/mtrr.h>
36 #include <cpu/k7/mtrr.h>
38 #define arraysize(x) (sizeof(x)/sizeof((x)[0]))
40 static unsigned int mtrr_msr[] = {
41 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
42 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
43 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
47 static void intel_enable_fixed_mtrr(void)
49 unsigned long low, high;
51 rdmsr(MTRRdefType_MSR, low, high);
53 wrmsr(MTRRdefType_MSR, low, high);
56 static void intel_enable_var_mtrr(void)
58 unsigned long low, high;
60 rdmsr(MTRRdefType_MSR, low, high);
62 wrmsr(MTRRdefType_MSR, low, high);
65 static inline void disable_cache(void)
69 /* Write back the cache and flush TLB */
72 "orl $0x40000000, %0\n\t"
80 static inline void enable_cache(void)
83 // turn cache back on.
86 "andl $0x9fffffff, %0\n\t"
92 /* setting variable mtrr, comes from linux kernel source */
93 static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
95 unsigned long base_high, base_low;
96 unsigned long mask_high, mask_low;
98 base_high = basek >> 22;
99 base_low = basek << 10;
101 if (sizek < 4*1024*1024) {
103 mask_low = ~((sizek << 10) -1);
106 mask_high = 0x0F & (~((sizek >> 22) -1));
113 // it is recommended that we disable and enable cache when we
117 /* The invalid bit is kept in the mask, so we simply clear the
118 relevant mask register to disable a range. */
119 wrmsr (MTRRphysMask_MSR (reg), 0, 0);
121 /* Bit 32-35 of MTRRphysMask should be set to 1 */
122 wrmsr (MTRRphysBase_MSR(reg), base_low | type, base_high);
123 wrmsr (MTRRphysMask_MSR(reg), mask_low | 0x800, mask_high);
128 /* setting variable mtrr, comes from linux kernel source */
129 void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
136 // it is recommended that we disable and enable cache when we
140 /* The invalid bit is kept in the mask, so we simply clear the
141 relevant mask register to disable a range. */
142 wrmsr (MTRRphysMask_MSR (reg), 0, 0);
144 /* Bit 32-35 of MTRRphysMask should be set to 1 */
145 wrmsr (MTRRphysBase_MSR (reg), base | type, 0);
146 wrmsr (MTRRphysMask_MSR (reg), ~(size - 1) | 0x800, 0x0F);
149 // turn cache back on.
153 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
154 static inline unsigned int fms(unsigned int x)
158 __asm__("bsrl %1,%0\n\t"
161 "1:" : "=r" (r) : "g" (x));
165 /* fms: find least sigificant bit set */
166 static inline unsigned int fls(unsigned int x)
170 __asm__("bsfl %1,%0\n\t"
173 "1:" : "=r" (r) : "g" (x));
177 /* setting up variable and fixed mtrr
179 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
180 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
181 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
182 * requirement. So a 8K range must be 8K aligned not 4K aligned.
184 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
185 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
186 * A 124MB (128MB - 4MB SMA) example:
187 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
188 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
190 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
191 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
192 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
193 * The same 124MB example:
194 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
195 * or a 156MB (128MB + 32MB - 4MB SMA) example:
196 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
198 /* 2 MTRRS are reserved for the operating system */
201 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
204 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
207 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
208 unsigned long low, high;
209 low = high = 0; /* Shut up gcc */
210 for(i = first; i < last; i++) {
211 /* When I switch to a new msr read it in */
212 if (fixed_msr != i >> 3) {
213 /* But first write out the old msr */
214 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
216 wrmsr(mtrr_msr[fixed_msr], low, high);
220 rdmsr(mtrr_msr[fixed_msr], low, high);
223 low &= ~(0xff << ((i&3)*8));
224 low |= type << ((i&3)*8);
226 high &= ~(0xff << ((i&3)*8));
227 high |= type << ((i&3)*8);
230 /* Write out the final msr */
231 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
233 wrmsr(mtrr_msr[fixed_msr], low, high);
238 static unsigned fixed_mtrr_index(unsigned long addrk)
241 index = (addrk - 0) >> 6;
243 index = ((addrk - 8*64) >> 4) + 8;
246 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
248 if (index > NUM_FIXED_RANGES) {
249 index = NUM_FIXED_RANGES;
254 static unsigned int range_to_mtrr(unsigned int reg,
255 unsigned long range_startk, unsigned long range_sizek,
256 unsigned long next_range_startk)
258 if (!range_sizek || (reg >= BIOS_MTRRS)) {
262 unsigned long max_align, align;
264 /* Compute the maximum size I can make a range */
265 max_align = fls(range_startk);
266 align = fms(range_sizek);
267 if (align > max_align) {
271 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
272 reg, range_startk >>10, sizek >> 10);
273 intel_set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
274 range_startk += sizek;
275 range_sizek -= sizek;
276 if (reg >= BIOS_MTRRS)
282 void setup_mtrrs(struct mem_range *mem)
284 /* Try this the simple way of incrementally adding together
285 * mtrrs. If this doesn't work out we can get smart again
286 * and clear out the mtrrs.
288 struct mem_range *memp;
289 unsigned long range_startk, range_sizek;
293 /* Initialized the fixed_mtrrs to uncached */
294 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
295 0, NUM_FIXED_RANGES);
296 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHABLE);
298 /* Now see which of the fixed mtrrs cover ram.
300 for(memp = mem; memp->sizek; memp++) {
301 unsigned int start_mtrr;
302 unsigned int last_mtrr;
303 start_mtrr = fixed_mtrr_index(memp->basek);
304 last_mtrr = fixed_mtrr_index(memp->basek + memp->sizek);
305 if (start_mtrr >= NUM_FIXED_RANGES) {
308 printk_debug("Setting fixed MTRRs(%d-%d) type: WB\n",
309 start_mtrr, last_mtrr);
310 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
312 printk_debug("DONE fixed MTRRs\n");
313 /* Cache as many memory areas as possible */
314 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
315 * In some cases it is definitely possible to do better.
320 for (memp = mem; memp->sizek; memp++) {
321 /* See if I can merge with the last range
322 * Either I am below 1M and the fixed mtrrs handle it, or
325 if ((memp->basek <= 1024) || (range_startk + range_sizek == memp->basek)) {
326 unsigned long endk = memp->basek + memp->sizek;
327 range_sizek = endk - range_startk;
330 /* Write the range mtrrs */
331 if (range_sizek != 0) {
332 reg = range_to_mtrr(reg, range_startk, range_sizek, memp->basek);
335 if (reg >= BIOS_MTRRS)
338 /* Allocate an msr */
339 range_startk = memp->basek;
340 range_sizek = memp->sizek;
342 /* Write the last range */
343 reg = range_to_mtrr(reg, range_startk, range_sizek, 0);
344 printk_debug("DONE variable MTRRs\n");
345 printk_debug("Clear out the extra MTRR's\n");
346 /* Clear out the extra MTRR's */
348 intel_set_var_mtrr(reg++, 0, 0, 0);
350 /* enable fixed MTRR */
351 printk_debug("call intel_enable_fixed_mtrr()\n");
352 intel_enable_fixed_mtrr();
353 printk_debug("call intel_enable_var_mtrr()\n");
354 intel_enable_var_mtrr();
355 printk_debug("Leave %s\n", __FUNCTION__);