2 * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
26 #include <console/console.h>
28 #include <cpu/p6/msr.h>
29 #include <cpu/p6/mtrr.h>
30 #include <cpu/k7/mtrr.h>
32 #define arraysize(x) (sizeof(x)/sizeof((x)[0]))
35 # define ADDRESS_BITS 40
37 # define ADDRESS_BITS 36
39 #define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
40 #define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
42 static unsigned int mtrr_msr[] = {
43 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
44 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
45 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
49 static void intel_enable_fixed_mtrr(void)
53 msr = rdmsr(MTRRdefType_MSR);
55 wrmsr(MTRRdefType_MSR, msr);
58 static void intel_enable_var_mtrr(void)
62 msr = rdmsr(MTRRdefType_MSR);
64 wrmsr(MTRRdefType_MSR, msr);
67 static inline void disable_cache(void)
71 /* Write back the cache and flush TLB */
74 "orl $0x40000000, %0\n\t"
82 static inline void enable_cache(void)
85 // turn cache back on.
88 "andl $0x9fffffff, %0\n\t"
94 /* setting variable mtrr, comes from linux kernel source */
95 static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
99 base.hi = basek >> 22;
100 base.lo = basek << 10;
102 //printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
104 if (sizek < 4*1024*1024) {
105 mask.hi = ADDRESS_MASK_HIGH;
106 mask.lo = ~((sizek << 10) -1);
109 mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
116 // it is recommended that we disable and enable cache when we
121 zero.lo = zero.hi = 0;
122 /* The invalid bit is kept in the mask, so we simply clear the
123 relevant mask register to disable a range. */
124 wrmsr (MTRRphysMask_MSR(reg), zero);
126 /* Bit 32-35 of MTRRphysMask should be set to 1 */
129 wrmsr (MTRRphysBase_MSR(reg), base);
130 wrmsr (MTRRphysMask_MSR(reg), mask);
135 /* setting variable mtrr, comes from linux kernel source */
136 void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
141 // it is recommended that we disable and enable cache when we
145 /* The invalid bit is kept in the mask, so we simply clear the
146 relevant mask register to disable a range. */
148 zero.lo = zero.hi = 0;
149 wrmsr (MTRRphysMask_MSR(reg), zero);
151 /* Bit 32-35 of MTRRphysMask should be set to 1 */
153 basem.lo = base | type;
155 maskm.lo = ~(size - 1) | 0x800;
157 wrmsr (MTRRphysBase_MSR(reg), basem);
158 wrmsr (MTRRphysMask_MSR(reg), maskm);
161 // turn cache back on.
165 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
166 static inline unsigned int fms(unsigned int x)
170 __asm__("bsrl %1,%0\n\t"
173 "1:" : "=r" (r) : "g" (x));
177 /* fms: find least sigificant bit set */
178 static inline unsigned int fls(unsigned int x)
182 __asm__("bsfl %1,%0\n\t"
185 "1:" : "=r" (r) : "g" (x));
189 /* setting up variable and fixed mtrr
191 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
192 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
193 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
194 * requirement. So a 8K range must be 8K aligned not 4K aligned.
196 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
197 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
198 * A 124MB (128MB - 4MB SMA) example:
199 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
200 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
202 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
203 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
204 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
205 * The same 124MB example:
206 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
207 * or a 156MB (128MB + 32MB - 4MB SMA) example:
208 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
210 /* 2 MTRRS are reserved for the operating system */
213 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
216 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
219 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
221 msr.lo = msr.hi = 0; /* Shut up gcc */
222 for (i = first; i < last; i++) {
223 /* When I switch to a new msr read it in */
224 if (fixed_msr != i >> 3) {
225 /* But first write out the old msr */
226 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
228 wrmsr(mtrr_msr[fixed_msr], msr);
232 msr = rdmsr(mtrr_msr[fixed_msr]);
235 msr.lo &= ~(0xff << ((i&3)*8));
236 msr.lo |= type << ((i&3)*8);
238 msr.hi &= ~(0xff << ((i&3)*8));
239 msr.hi |= type << ((i&3)*8);
242 /* Write out the final msr */
243 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
245 wrmsr(mtrr_msr[fixed_msr], msr);
250 static unsigned fixed_mtrr_index(unsigned long addrk)
253 index = (addrk - 0) >> 6;
255 index = ((addrk - 8*64) >> 4) + 8;
258 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
260 if (index > NUM_FIXED_RANGES) {
261 index = NUM_FIXED_RANGES;
266 static unsigned int range_to_mtrr(unsigned int reg,
267 unsigned long range_startk, unsigned long range_sizek,
268 unsigned long next_range_startk)
270 if (!range_sizek || (reg >= BIOS_MTRRS)) {
274 unsigned long max_align, align;
276 /* Compute the maximum size I can make a range */
277 max_align = fls(range_startk);
278 align = fms(range_sizek);
279 if (align > max_align) {
283 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
284 reg, range_startk >>10, sizek >> 10);
285 intel_set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
286 range_startk += sizek;
287 range_sizek -= sizek;
288 if (reg >= BIOS_MTRRS)
294 void setup_mtrrs(struct mem_range *mem)
296 /* Try this the simple way of incrementally adding together
297 * mtrrs. If this doesn't work out we can get smart again
298 * and clear out the mtrrs.
300 struct mem_range *memp;
301 unsigned long range_startk, range_sizek;
305 #if defined(k7) || defined(k8)
306 /* Enable the access to AMD RdDram and WrDram extension bits */
307 msr = rdmsr(SYSCFG_MSR);
308 msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
309 wrmsr(SYSCFG_MSR, msr);
313 /* Initialized the fixed_mtrrs to uncached */
314 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
315 0, NUM_FIXED_RANGES);
316 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
318 /* Now see which of the fixed mtrrs cover ram.
320 for (memp = mem; memp->sizek; memp++) {
321 unsigned int start_mtrr;
322 unsigned int last_mtrr;
323 start_mtrr = fixed_mtrr_index(memp->basek);
324 last_mtrr = fixed_mtrr_index(memp->basek + memp->sizek);
325 if (start_mtrr >= NUM_FIXED_RANGES) {
329 printk_debug("Setting fixed MTRRs(%d-%d) type: WB\n",
330 start_mtrr, last_mtrr);
333 #if defined(k7) || defined(k8)
334 set_fixed_mtrrs(start_mtrr, last_mtrr,
335 MTRR_TYPE_WRBACK | MTRR_READ_MEM| MTRR_WRITE_MEM);
337 set_fixed_mtrrs(start_mtrr, last_mtrr,
341 printk_debug("DONE fixed MTRRs\n");
343 #if defined(k7) || defined(k8)
344 /* Disable the access to AMD RdDram and WrDram extension bits */
345 msr = rdmsr(SYSCFG_MSR);
346 msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
347 wrmsr(SYSCFG_MSR, msr);
348 /* Enale the RdMEM and WrMEM bits in SYSCFG */
349 msr = rdmsr(SYSCFG_MSR);
350 msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
351 wrmsr(SYSCFG_MSR, msr);
354 /* Cache as many memory areas as possible */
355 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
356 * In some cases it is definitely possible to do better.
361 for (memp = mem; memp->sizek; memp++) {
362 /* See if I can merge with the last range
363 * Either I am below 1M and the fixed mtrrs handle it, or
366 if ((memp->basek <= 1024) || (range_startk + range_sizek == memp->basek)) {
367 unsigned long endk = memp->basek + memp->sizek;
368 range_sizek = endk - range_startk;
371 /* Write the range mtrrs */
372 if (range_sizek != 0) {
373 reg = range_to_mtrr(reg, range_startk, range_sizek, memp->basek);
376 if (reg >= BIOS_MTRRS)
379 /* Allocate an msr */
380 range_startk = memp->basek;
381 range_sizek = memp->sizek;
383 /* Write the last range */
384 reg = range_to_mtrr(reg, range_startk, range_sizek, 0);
385 printk_debug("DONE variable MTRRs\n");
386 printk_debug("Clear out the extra MTRR's\n");
387 /* Clear out the extra MTRR's */
389 intel_set_var_mtrr(reg++, 0, 0, 0);
391 /* enable fixed MTRR */
392 printk_debug("call intel_enable_fixed_mtrr()\n");
393 intel_enable_fixed_mtrr();
394 printk_debug("call intel_enable_var_mtrr()\n");
395 intel_enable_var_mtrr();
396 printk_debug("Leave %s\n", __FUNCTION__);