src/cpu/intel/speedstep/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 #include <types.h>
  23 #include <console/console.h>
  24 #include <arch/acpi.h>
  25 #include <arch/acpigen.h>
  26 #include <arch/cpu.h>
  27 #include <cpu/x86/msr.h>
  28 #include <cpu/intel/acpi.h>
  29 #include <device/device.h>
  30
  31 // XXX: PSS table values for power consumption are for Merom only
  32
  33 static int determine_total_number_of_cores(void)
  34 {
  35         device_t cpu;
  36         int count = 0;
  37         for(cpu = all_devices; cpu; cpu = cpu->next) {
  38                 if ((cpu->path.type != DEVICE_PATH_APIC) ||
  39                         (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
  40                         continue;
  41                 }
  42                 if (!cpu->enabled) {
  43                         continue;
  44                 }
  45                 count++;
  46         }
  47         return count;
  48 }
  49
  50 static int get_fsb(void)
  51 {
  52         u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7;
  53         switch (fsbcode) {
  54                 case 0: return 266;
  55                 case 1: return 133;
  56                 case 2: return 200;
  57                 case 3: return 166;
  58                 case 5: return 100;
  59         }
  60         printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
  61         return 200;
  62 }
  63
  64 void generate_cpu_entries(void)
  65 {
  66         int len_pr, len_ps;
  67         int coreID, cpuID, pcontrol_blk=0x510, plen=6;
  68         msr_t msr;
  69         int totalcores = determine_total_number_of_cores();
  70         int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
  71         int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
  72         printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
  73
  74         for (cpuID=1; cpuID <=numcpus; cpuID++) {
  75                 for (coreID=1; coreID<=cores_per_package; coreID++) {
  76                 if (coreID>1) {
  77                         pcontrol_blk = 0;
  78                         plen = 0;
  79                 }
  80                 len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
  81                         len_pr += acpigen_write_empty_PCT();
  82                         len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
  83                         len_pr += acpigen_write_name("_PSS");
  84
  85                         int max_states=8;
  86                         int busratio_step=2;
  87                         msr = rdmsr(IA32_PERF_STS);
  88                         int busratio_min=(msr.lo >> 24) & 0x1f;
  89                         int busratio_max=(msr.hi >> (40-32)) & 0x1f;
  90                         int vid_min=msr.lo & 0x3f;
  91                         msr = rdmsr(IA32_PLATFORM_ID);
  92                         int vid_max=msr.lo & 0x3f;
  93                         int clock_max=get_fsb()*busratio_max;
  94                         int clock_min=get_fsb()*busratio_min;
  95                         printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
  96 #define MEROM_MIN_POWER 16000
  97 #define MEROM_MAX_POWER 35000
  98                         int power_max=MEROM_MAX_POWER;
  99                         int power_min=MEROM_MIN_POWER;
 100
 101                         int num_states=(busratio_max-busratio_min)/busratio_step;
 102                         while (num_states > max_states-1) {
 103                                 busratio_step <<= 1;
 104                                 num_states >>= 1;
 105                         }
 106                         printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max);
 107                         int vid_step=(vid_max-vid_min)/num_states;
 108                         int power_step=(power_max-power_min)/num_states;
 109                         int clock_step=(clock_max-clock_min)/num_states;
 110                         len_ps = acpigen_write_package(num_states+1); // for Super LFM, this must be increases by another one
 111                         len_ps += acpigen_write_PSS_package(clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (busratio_max<<8)|(vid_max) /*control*/, (busratio_max<<8)|(vid_max) /*status*/);
 112                         int current_busratio=busratio_min+((num_states-1)*busratio_step);
 113                         int current_vid=vid_min+((num_states-1)*vid_step);
 114                         int current_power=power_min+((num_states-1)*power_step);
 115                         int current_clock=clock_min+((num_states-1)*clock_step);
 116                         int i;
 117                         for (i=0;i<num_states; i++) {
 118                                 len_ps += acpigen_write_PSS_package(current_clock /*mhz*/, current_power /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (current_busratio<<8)|(current_vid) /*control*/, (current_busratio<<8)|(current_vid) /*status*/);
 119                                 current_busratio -= busratio_step;
 120                                 current_vid -= vid_step;
 121                                 current_power -= power_step;
 122                                 current_clock -= clock_step;
 123                         }
 124                         len_ps--;
 125                         acpigen_patch_len(len_ps);
 126                         len_pr += acpigen_write_PPC(0);
 127                 len_pr += len_ps;
 128                 len_pr--;
 129                 acpigen_patch_len(len_pr);
 130                 }
 131         }
 132 }
 133