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HEAD
- With Xeon cpus it seems best to use the tsc calibrated with timer2 as
[coreboot.git]
/
src
/
cpu
/
intel
/
model_f2x
/
Config.lb
1
dir /cpu/x86/mtrr
2
dir /cpu/x86/fpu
3
dir /cpu/x86/mmx
4
dir /cpu/x86/sse
5
dir /cpu/x86/lapic
6
dir /cpu/x86/cache
7
dir /cpu/intel/microcode
8
dir /cpu/intel/hyperthreading
9
driver model_f2x_init.o
10