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HEAD
Intel cpus: cache actual size of the Flash ROM device
[coreboot.git]
/
src
/
cpu
/
intel
/
model_6ex
/
Kconfig
1
config CPU_INTEL_MODEL_6EX
2
bool
3
select SMP
4
select SSE2
5
select UDELAY_LAPIC
6
select AP_IN_SIPI_WAIT