2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2007-2008 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/stack.h>
22 #include <cpu/x86/mtrr.h>
23 #include <cpu/x86/post_code.h>
25 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
26 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
28 /* Save the BIST result. */
34 /* Send INIT IPI to all excluding ourself. */
35 movl $0x000C4500, %eax
36 movl $0xFEE00300, %esi
39 /* Zero out all fixed range and variable range MTRRs. */
40 movl $mtrr_table, %esi
41 movl $((mtrr_table_end - mtrr_table) / 2), %edi
52 /* Configure the default memory type to uncacheable. */
53 movl $MTRRdefType_MSR, %ecx
55 andl $(~0x00000cff), %eax
58 /* Set Cache-as-RAM base address. */
59 movl $(MTRRphysBase_MSR(0)), %ecx
60 movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
64 /* Set Cache-as-RAM mask. */
65 movl $(MTRRphysMask_MSR(0)), %ecx
66 movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
71 movl $MTRRdefType_MSR, %ecx
73 orl $MTRRdefTypeEn, %eax
76 /* Enable L2 cache. */
82 /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
84 andl $(~((1 << 30) | (1 << 29))), %eax
88 /* Clear the cache memory reagion. */
89 movl $CACHE_AS_RAM_BASE, %esi
91 movl $(CACHE_AS_RAM_SIZE / 4), %ecx
92 // movl $0x23322332, %eax
96 /* Enable Cache-as-RAM mode by disabling cache. */
101 #if CONFIG_XIP_ROM_SIZE
102 /* Enable cache for our code in Flash because we do XIP here */
103 movl $MTRRphysBase_MSR(1), %ecx
106 * IMPORTANT: The following calculation _must_ be done at runtime. See
107 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
109 movl $copy_and_run, %eax
110 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
111 orl $MTRR_TYPE_WRBACK, %eax
114 movl $MTRRphysMask_MSR(1), %ecx
116 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
118 #endif /* CONFIG_XIP_ROM_SIZE */
122 andl $(~((1 << 30) | (1 << 29))), %eax
125 /* Set up the stack pointer. */
127 /* Leave some space for the struct ehci_debug_info. */
128 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
130 movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
134 /* Restore the BIST result. */
141 /* Call romstage.c main function. */
156 movl $MTRRdefType_MSR, %ecx
158 andl $(~MTRRdefTypeEn), %eax
167 movl $MTRRphysBase_MSR(0), %ecx
169 movl $MTRRphysMask_MSR(0), %ecx
171 movl $MTRRphysBase_MSR(1), %ecx
173 movl $MTRRphysMask_MSR(1), %ecx
181 andl $~((1 << 30) | (1 << 29)), %eax
193 /* Enable Write Back and Speculative Reads for the first 1MB. */
194 movl $MTRRphysBase_MSR(0), %ecx
195 movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
198 movl $MTRRphysMask_MSR(0), %ecx
199 movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
205 /* And enable cache again after setting MTRRs. */
207 andl $~((1 << 30) | (1 << 29)), %eax
213 movl $MTRRdefType_MSR, %ecx
215 orl $MTRRdefTypeEn, %eax
220 /* Invalidate the cache again. */
225 /* Clear boot_complete flag. */
228 post_code(POST_PREPARE_RAMSTAGE)
229 cld /* Clear direction flag. */
233 movl $ROMSTAGE_STACK, %esp
239 post_code(POST_DEAD_CODE)
245 .word 0x250, 0x258, 0x259
246 .word 0x268, 0x269, 0x26A
247 .word 0x26B, 0x26C, 0x26D
250 .word 0x200, 0x201, 0x202, 0x203
251 .word 0x204, 0x205, 0x206, 0x207
252 .word 0x208, 0x209, 0x20A, 0x20B
253 .word 0x20C, 0x20D, 0x20E, 0x20F