2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
27 #include <cpu/x86/mtrr.h>
28 #include <cpu/x86/msr.h>
29 #include <cpu/x86/lapic.h>
30 #include <cpu/intel/microcode.h>
31 #include <cpu/intel/speedstep.h>
32 #include <cpu/intel/hyperthreading.h>
33 #include <cpu/x86/cache.h>
34 #include <cpu/x86/name.h>
36 static const uint32_t microcode_updates[] = {
37 #include "microcode-2618-m441067AA07.h"
38 #include "microcode-2626-m1010677705.h"
39 #include "microcode-2498-m101067660C.h"
40 #include "microcode-2497-m041067660C.h"
41 #include "microcode-2499-m401067660C.h"
42 #include "microcode-2617-m111067AA07.h"
43 #include "microcode-2619-mA01067AA07.h"
44 #include "microcode-2623-m011067660C.h"
45 #include "microcode-2501-m801067660C.h"
47 /* Dummy terminator */
54 static void init_timer(void)
56 /* Set the apic timer to no interrupts and periodic mode */
57 lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
59 /* Set the divider to 1, no divider */
60 lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
62 /* Set the initial counter to 0xffffffff */
63 lapic_write(LAPIC_TMICT, 0xffffffff);
66 #define IA32_FEATURE_CONTROL 0x003a
68 #define CPUID_VMX (1 << 5)
69 #define CPUID_SMX (1 << 6)
70 static void enable_vmx(void)
72 struct cpuid_result regs;
75 msr = rdmsr(IA32_FEATURE_CONTROL);
77 if (msr.lo & (1 << 0)) {
78 /* VMX locked. If we set it again we get an illegal
85 if (regs.ecx & CPUID_VMX) {
87 if (regs.ecx & CPUID_SMX)
91 wrmsr(IA32_FEATURE_CONTROL, msr);
93 msr.lo |= (1 << 0); /* Set lock bit */
95 wrmsr(IA32_FEATURE_CONTROL, msr);
98 #define PMG_CST_CONFIG_CONTROL 0xe2
99 #define PMG_IO_BASE_ADDR 0xe3
100 #define PMG_IO_CAPTURE_ADDR 0xe4
103 static void configure_c_states(void)
107 msr = rdmsr(PMG_CST_CONFIG_CONTROL);
109 msr.lo |= (1 << 15); // config lock until next reset
110 msr.lo |= (1 << 14); // Deeper Sleep
111 msr.lo |= (1 << 10); // Enable IO MWAIT redirection
112 msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
113 msr.lo |= (1 << 3); // Dynamic L2
115 wrmsr(PMG_CST_CONFIG_CONTROL, msr);
117 /* Set Processor MWAIT IO BASE */
119 msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
120 wrmsr(PMG_IO_BASE_ADDR, msr);
122 /* Set IO Capture Address */
124 msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16);
125 wrmsr(PMG_IO_CAPTURE_ADDR, msr);
128 #define IA32_MISC_ENABLE 0x1a0
129 static void configure_misc(void)
133 msr = rdmsr(IA32_MISC_ENABLE);
134 msr.lo |= (1 << 3); /* TM1 enable */
135 msr.lo |= (1 << 13); /* TM2 enable */
136 msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
138 msr.lo |= (1 << 10); /* FERR# multiplexing */
140 // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
141 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
147 /* TODO This should only be done on mobile CPUs, see cpuid 5 */
148 msr.hi |= (1 << (32 - 32)); // C4E
149 msr.hi |= (1 << (33 - 32)); // Hard C4E
152 /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */
153 msr.hi |= (1 << (36 - 32));
155 wrmsr(IA32_MISC_ENABLE, msr);
157 msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
158 wrmsr(IA32_MISC_ENABLE, msr);
161 #define PIC_SENS_CFG 0x1aa
162 static void configure_pic_thermal_sensors(void)
166 msr = rdmsr(PIC_SENS_CFG);
168 msr.lo |= (1 << 21); // inter-core lock TM1
169 msr.lo |= (1 << 4); // Enable bypass filter
171 wrmsr(PIC_SENS_CFG, msr);
175 static unsigned ehci_debug_addr;
178 static void model_1067x_init(device_t cpu)
180 char processor_name[49];
182 /* Turn on caching if we haven't already */
185 /* Update the microcode */
186 intel_update_microcode(microcode_updates);
188 /* Print processor name */
189 fill_processor_name(processor_name);
190 printk(BIOS_INFO, "CPU: %s.\n", processor_name);
193 // Is this caution really needed?
195 ehci_debug_addr = get_ehci_debug();
204 set_ehci_debug(ehci_debug_addr);
207 /* Enable the local cpu apics */
210 /* Initialize the APIC timer */
213 /* Enable virtualization */
216 /* Configure C States */
217 configure_c_states();
219 /* Configure Enhanced SpeedStep and Thermal Sensors */
222 /* PIC thermal sensor control */
223 configure_pic_thermal_sensors();
225 /* Start up my cpu siblings */
226 intel_sibling_init(cpu);
229 static struct device_operations cpu_dev_ops = {
230 .init = model_1067x_init,
233 static struct cpu_device_id cpu_table[] = {
234 { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */
235 { X86_VENDOR_INTEL, 0x10677 },
236 { X86_VENDOR_INTEL, 0x1067A },
240 static const struct cpu_driver driver __cpu_driver = {
242 .id_table = cpu_table,