1 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
15 void sc520_udelay(int microseconds) {
17 for(x = 0; x < 1000; x++)
21 /* looks like we define this now */
23 udelay(int microseconds) {
24 sc520_udelay(microseconds);
27 * set up basic things ... PAR should NOT go here, as it might change with the mainboard.
29 static void cpu_init(device_t dev)
31 unsigned long *l = (unsigned long *) 0xfffef088;
33 for(i = 0; i < 16; i++, l++)
34 printk_err("Par%d: 0x%lx\n", i, *l);
36 printk_spew("SC520 random fixup ...\n");
40 /* Ollie says: make a northbridge/amd/sc520. Ron sez:
41 * there is no real northbridge, keep it here in cpu.
42 * Ron wins, he's writing the code.
44 void sc520_enable_resources(struct device *dev) {
45 unsigned char command;
47 printk_spew("%s\n", __FUNCTION__);
48 command = pci_read_config8(dev, PCI_COMMAND);
49 printk_spew("========>%s, command 0x%x\n", __FUNCTION__, command);
50 command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
51 printk_spew("========>%s, command 0x%x\n", __FUNCTION__, command);
52 pci_write_config8(dev, PCI_COMMAND, command);
53 command = pci_read_config8(dev, PCI_COMMAND);
54 printk_spew("========>%s, command 0x%x\n", __FUNCTION__, command);
61 static struct device_operations cpu_operations = {
62 .read_resources = pci_dev_read_resources,
63 .set_resources = pci_dev_set_resources,
64 .enable_resources = sc520_enable_resources,
70 static struct pci_driver cpu_driver __pci_driver = {
71 .ops = &cpu_operations,
72 .vendor = PCI_VENDOR_ID_AMD,
78 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
80 static void pci_domain_read_resources(device_t dev)
82 struct resource *resource;
83 printk_spew("%s\n", __FUNCTION__);
84 /* Initialize the system wide io space constraints */
85 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
86 resource->limit = 0xffffUL;
87 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
89 /* Initialize the system wide memory resources constraints */
90 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
91 resource->limit = 0xffffffffULL;
92 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
95 static void ram_resource(device_t dev, unsigned long index,
96 unsigned long basek, unsigned long sizek)
98 struct resource *resource;
99 printk_spew("%s sizek 0x%x\n", __FUNCTION__, sizek);
103 resource = new_resource(dev, index);
104 resource->base = ((resource_t)basek) << 10;
105 resource->size = ((resource_t)sizek) << 10;
106 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
107 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
110 static void tolm_test(void *gp, struct device *dev, struct resource *new)
112 struct resource **best_p = gp;
113 struct resource *best;
115 if (!best || (best->base > new->base)) {
121 static uint32_t find_pci_tolm(struct bus *bus)
123 struct resource *min;
125 printk_spew("%s\n", __FUNCTION__);
127 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
129 if (min && tolm > min->base) {
132 printk_spew("%s returns 0x%x\n", __FUNCTION__, tolm);
136 static void pci_domain_set_resources(device_t dev)
140 printk_spew("%s\n", __FUNCTION__);
141 pci_tolm = find_pci_tolm(&dev->link[0]);
142 mc_dev = dev->link[0].children;
144 unsigned long tomk, tolmk;
145 // unsigned char rambits;
149 for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
151 reg = pci_read_config8(mc_dev, ramregs[i]);
152 /* these are ENDING addresses, not sizes.
153 * if there is memory in this slot, then reg will be > rambits.
154 * So we just take the max, that gives us total.
155 * We take the highest one to cover for once and future linuxbios
156 * bugs. We warn about bugs.
161 printk_err("ERROR! register 0x%x is not set!\n",
164 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
165 tomk = rambits*8*1024;
168 /* Compute the top of Low memory */
169 tolmk = pci_tolm >> 10;
171 /* The PCI hole does does not overlap the memory.
175 /* Report the memory regions */
177 ram_resource(dev, idx++, 0, tolmk);
179 assign_resources(&dev->link[0]);
182 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
184 printk_spew("%s\n", __FUNCTION__);
185 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
191 void sc520_enable_resources(device_t dev) {
193 printk_spew("%s\n", __FUNCTION__);
194 printk_spew("THIS IS FOR THE SC520 =============================\n");
197 command = pci_read_config8(dev, PCI_COMMAND);
198 printk_spew("%s, command 0x%x\n", __FUNCTION__, command);
199 command |= PCI_COMMAND_MEMORY;
200 printk_spew("%s, command 0x%x\n", __FUNCTION__, command);
201 pci_write_config8(dev, PCI_COMMAND, command);
202 command = pci_read_config8(dev, PCI_COMMAND);
203 printk_spew("%s, command 0x%x\n", __FUNCTION__, command);
205 enable_childrens_resources(dev);
206 printk_spew("%s\n", __FUNCTION__);
210 static struct device_operations pci_domain_ops = {
211 .read_resources = pci_domain_read_resources,
212 .set_resources = pci_domain_set_resources,
213 .enable_resources = enable_resources,
215 .scan_bus = pci_domain_scan_bus,
218 static void cpu_bus_init(device_t dev)
220 printk_spew("cpu_bus_init\n");
223 static void cpu_bus_noop(device_t dev)
227 static struct device_operations cpu_bus_ops = {
228 .read_resources = cpu_bus_noop,
229 .set_resources = cpu_bus_noop,
230 .enable_resources = cpu_bus_noop,
231 .init = cpu_bus_init,
235 static void enable_dev(struct device *dev)
237 printk_spew("%s\n", __FUNCTION__);
238 /* Set the operations if it is a special bus type */
239 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
240 dev->ops = &pci_domain_ops;
243 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
244 dev->ops = &cpu_bus_ops;
249 struct chip_operations cpu_amd_sc520_ops = {
250 CHIP_NAME("AMD SC520")
251 .enable_dev = enable_dev,